297 lines
7.3 KiB
C
297 lines
7.3 KiB
C
/*
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* Atmel PIO4 device driver
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*
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* Copyright (C) 2015 Atmel Corporation
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* Wenyou.Yang <wenyou.yang@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/arch/hardware.h>
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#include <mach/gpio.h>
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#include <mach/atmel_pio4.h>
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#define ATMEL_PIO4_PINS_PER_BANK 32
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/*
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* Register Field Definitions
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*/
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#define ATMEL_PIO4_CFGR_FUNC (0x7 << 0)
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#define ATMEL_PIO4_CFGR_FUNC_GPIO (0x0 << 0)
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#define ATMEL_PIO4_CFGR_FUNC_PERIPH_A (0x1 << 0)
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#define ATMEL_PIO4_CFGR_FUNC_PERIPH_B (0x2 << 0)
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#define ATMEL_PIO4_CFGR_FUNC_PERIPH_C (0x3 << 0)
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#define ATMEL_PIO4_CFGR_FUNC_PERIPH_D (0x4 << 0)
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#define ATMEL_PIO4_CFGR_FUNC_PERIPH_E (0x5 << 0)
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#define ATMEL_PIO4_CFGR_FUNC_PERIPH_F (0x6 << 0)
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#define ATMEL_PIO4_CFGR_FUNC_PERIPH_G (0x7 << 0)
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#define ATMEL_PIO4_CFGR_DIR (0x1 << 8)
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#define ATMEL_PIO4_CFGR_PUEN (0x1 << 9)
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#define ATMEL_PIO4_CFGR_PDEN (0x1 << 10)
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#define ATMEL_PIO4_CFGR_IFEN (0x1 << 12)
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#define ATMEL_PIO4_CFGR_IFSCEN (0x1 << 13)
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#define ATMEL_PIO4_CFGR_OPD (0x1 << 14)
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#define ATMEL_PIO4_CFGR_SCHMITT (0x1 << 15)
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#define ATMEL_PIO4_CFGR_DRVSTR (0x3 << 16)
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#define ATMEL_PIO4_CFGR_DRVSTR_LOW0 (0x0 << 16)
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#define ATMEL_PIO4_CFGR_DRVSTR_LOW1 (0x1 << 16)
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#define ATMEL_PIO4_CFGR_DRVSTR_MEDIUM (0x2 << 16)
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#define ATMEL_PIO4_CFGR_DRVSTR_HIGH (0x3 << 16)
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#define ATMEL_PIO4_CFGR_EVTSEL (0x7 << 24)
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#define ATMEL_PIO4_CFGR_EVTSEL_FALLING (0x0 << 24)
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#define ATMEL_PIO4_CFGR_EVTSEL_RISING (0x1 << 24)
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#define ATMEL_PIO4_CFGR_EVTSEL_BOTH (0x2 << 24)
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#define ATMEL_PIO4_CFGR_EVTSEL_LOW (0x3 << 24)
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#define ATMEL_PIO4_CFGR_EVTSEL_HIGH (0x4 << 24)
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#define ATMEL_PIO4_CFGR_PCFS (0x1 << 29)
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#define ATMEL_PIO4_CFGR_ICFS (0x1 << 30)
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static struct atmel_pio4_port *atmel_pio4_port_base(u32 port)
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{
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struct atmel_pio4_port *base = NULL;
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switch (port) {
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case AT91_PIO_PORTA:
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base = (struct atmel_pio4_port *)ATMEL_BASE_PIOA;
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break;
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case AT91_PIO_PORTB:
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base = (struct atmel_pio4_port *)ATMEL_BASE_PIOB;
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break;
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case AT91_PIO_PORTC:
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base = (struct atmel_pio4_port *)ATMEL_BASE_PIOC;
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break;
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case AT91_PIO_PORTD:
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base = (struct atmel_pio4_port *)ATMEL_BASE_PIOD;
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break;
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default:
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printf("Error: Atmel PIO4: Failed to get PIO base of port#%d!\n",
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port);
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break;
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}
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return base;
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}
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static int atmel_pio4_config_io_func(u32 port, u32 pin,
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u32 func, u32 use_pullup)
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{
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struct atmel_pio4_port *port_base;
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u32 reg, mask;
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if (pin >= ATMEL_PIO4_PINS_PER_BANK)
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return -ENODEV;
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port_base = atmel_pio4_port_base(port);
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if (!port_base)
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return -ENODEV;
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mask = 1 << pin;
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reg = func;
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reg |= use_pullup ? ATMEL_PIO4_CFGR_PUEN : 0;
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writel(mask, &port_base->mskr);
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writel(reg, &port_base->cfgr);
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return 0;
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}
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int atmel_pio4_set_gpio(u32 port, u32 pin, u32 use_pullup)
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{
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return atmel_pio4_config_io_func(port, pin,
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ATMEL_PIO4_CFGR_FUNC_GPIO,
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use_pullup);
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}
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int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 use_pullup)
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{
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return atmel_pio4_config_io_func(port, pin,
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ATMEL_PIO4_CFGR_FUNC_PERIPH_A,
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use_pullup);
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}
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int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 use_pullup)
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{
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return atmel_pio4_config_io_func(port, pin,
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ATMEL_PIO4_CFGR_FUNC_PERIPH_B,
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use_pullup);
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}
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int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 use_pullup)
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{
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return atmel_pio4_config_io_func(port, pin,
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ATMEL_PIO4_CFGR_FUNC_PERIPH_C,
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use_pullup);
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}
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int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 use_pullup)
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{
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return atmel_pio4_config_io_func(port, pin,
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ATMEL_PIO4_CFGR_FUNC_PERIPH_D,
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use_pullup);
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}
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int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 use_pullup)
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{
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return atmel_pio4_config_io_func(port, pin,
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ATMEL_PIO4_CFGR_FUNC_PERIPH_E,
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use_pullup);
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}
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int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 use_pullup)
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{
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return atmel_pio4_config_io_func(port, pin,
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ATMEL_PIO4_CFGR_FUNC_PERIPH_F,
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use_pullup);
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}
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int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 use_pullup)
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{
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return atmel_pio4_config_io_func(port, pin,
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ATMEL_PIO4_CFGR_FUNC_PERIPH_G,
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use_pullup);
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}
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int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value)
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{
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struct atmel_pio4_port *port_base;
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u32 reg, mask;
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if (pin >= ATMEL_PIO4_PINS_PER_BANK)
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return -ENODEV;
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port_base = atmel_pio4_port_base(port);
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if (!port_base)
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return -ENODEV;
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mask = 0x01 << pin;
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reg = ATMEL_PIO4_CFGR_FUNC_GPIO | ATMEL_PIO4_CFGR_DIR;
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writel(mask, &port_base->mskr);
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writel(reg, &port_base->cfgr);
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if (value)
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writel(mask, &port_base->sodr);
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else
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writel(mask, &port_base->codr);
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return 0;
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}
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int atmel_pio4_get_pio_input(u32 port, u32 pin)
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{
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struct atmel_pio4_port *port_base;
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u32 reg, mask;
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if (pin >= ATMEL_PIO4_PINS_PER_BANK)
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return -ENODEV;
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port_base = atmel_pio4_port_base(port);
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if (!port_base)
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return -ENODEV;
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mask = 0x01 << pin;
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reg = ATMEL_PIO4_CFGR_FUNC_GPIO;
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writel(mask, &port_base->mskr);
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writel(reg, &port_base->cfgr);
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return (readl(&port_base->pdsr) & mask) ? 1 : 0;
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}
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#ifdef CONFIG_DM_GPIO
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static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset)
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{
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struct at91_port_platdata *plat = dev_get_platdata(dev);
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struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
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u32 mask = 0x01 << offset;
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u32 reg = ATMEL_PIO4_CFGR_FUNC_GPIO;
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writel(mask, &port_base->mskr);
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writel(reg, &port_base->cfgr);
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return 0;
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}
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static int atmel_pio4_direction_output(struct udevice *dev,
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unsigned offset, int value)
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{
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struct at91_port_platdata *plat = dev_get_platdata(dev);
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struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
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u32 mask = 0x01 << offset;
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u32 reg = ATMEL_PIO4_CFGR_FUNC_GPIO | ATMEL_PIO4_CFGR_DIR;
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writel(mask, &port_base->mskr);
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writel(reg, &port_base->cfgr);
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if (value)
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writel(mask, &port_base->sodr);
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else
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writel(mask, &port_base->codr);
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return 0;
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}
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static int atmel_pio4_get_value(struct udevice *dev, unsigned offset)
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{
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struct at91_port_platdata *plat = dev_get_platdata(dev);
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struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
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u32 mask = 0x01 << offset;
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return (readl(&port_base->pdsr) & mask) ? 1 : 0;
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}
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static int atmel_pio4_set_value(struct udevice *dev,
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unsigned offset, int value)
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{
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struct at91_port_platdata *plat = dev_get_platdata(dev);
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struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
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u32 mask = 0x01 << offset;
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if (value)
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writel(mask, &port_base->sodr);
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else
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writel(mask, &port_base->codr);
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return 0;
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}
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static int atmel_pio4_get_function(struct udevice *dev, unsigned offset)
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{
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struct at91_port_platdata *plat = dev_get_platdata(dev);
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struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
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u32 mask = 0x01 << offset;
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writel(mask, &port_base->mskr);
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return (readl(&port_base->cfgr) &
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ATMEL_PIO4_CFGR_DIR) ? GPIOF_OUTPUT : GPIOF_INPUT;
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}
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static const struct dm_gpio_ops atmel_pio4_ops = {
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.direction_input = atmel_pio4_direction_input,
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.direction_output = atmel_pio4_direction_output,
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.get_value = atmel_pio4_get_value,
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.set_value = atmel_pio4_set_value,
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.get_function = atmel_pio4_get_function,
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};
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static int atmel_pio4_probe(struct udevice *dev)
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{
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struct at91_port_platdata *plat = dev_get_platdata(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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uc_priv->bank_name = plat->bank_name;
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uc_priv->gpio_count = ATMEL_PIO4_PINS_PER_BANK;
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return 0;
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}
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U_BOOT_DRIVER(gpio_atmel_pio4) = {
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.name = "gpio_atmel_pio4",
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.id = UCLASS_GPIO,
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.ops = &atmel_pio4_ops,
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.probe = atmel_pio4_probe,
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};
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#endif
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