139 lines
3.4 KiB
C
139 lines
3.4 KiB
C
/*
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* Keystone2: get clk rate for K2L
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clock_defs.h>
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const struct keystone_pll_regs keystone_pll_regs[] = {
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[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
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[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
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[TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
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[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
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};
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int dev_speeds[] = {
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SPD800,
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SPD1000,
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SPD1200,
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SPD800,
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SPD800,
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SPD800,
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SPD800,
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SPD800,
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SPD1200,
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SPD1000,
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SPD800,
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SPD800,
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SPD800,
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};
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int arm_speeds[] = {
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SPD800,
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SPD1000,
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SPD1200,
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SPD1350,
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SPD1400,
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SPD800,
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SPD1400,
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SPD1350,
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SPD1200,
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SPD1000,
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SPD800,
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SPD800,
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SPD800,
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};
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/**
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* pll_freq_get - get pll frequency
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* Fout = Fref * NF(mult) / NR(prediv) / OD
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* @pll: pll identifier
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*/
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static unsigned long pll_freq_get(int pll)
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{
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unsigned long mult = 1, prediv = 1, output_div = 2;
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unsigned long ret;
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u32 tmp, reg;
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if (pll == CORE_PLL) {
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ret = external_clk[sys_clk];
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if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
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/* PLL mode */
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tmp = __raw_readl(KS2_MAINPLLCTL0);
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prediv = (tmp & PLL_DIV_MASK) + 1;
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mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
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(pllctl_reg_read(pll, mult) &
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PLLM_MULT_LO_MASK)) + 1;
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output_div = ((pllctl_reg_read(pll, secctl) >>
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PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
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ret = ret / prediv / output_div * mult;
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}
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} else {
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switch (pll) {
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case PASS_PLL:
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ret = external_clk[pa_clk];
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reg = KS2_PASSPLLCTL0;
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break;
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case TETRIS_PLL:
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ret = external_clk[tetris_clk];
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reg = KS2_ARMPLLCTL0;
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break;
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case DDR3_PLL:
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ret = external_clk[ddr3_clk];
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reg = KS2_DDR3APLLCTL0;
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break;
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default:
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return 0;
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}
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tmp = __raw_readl(reg);
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if (!(tmp & PLLCTL_BYPASS)) {
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/* Bypass disabled */
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prediv = (tmp & PLL_DIV_MASK) + 1;
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mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
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output_div = ((tmp >> PLL_CLKOD_SHIFT) &
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PLL_CLKOD_MASK) + 1;
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ret = ((ret / prediv) * mult) / output_div;
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}
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}
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return ret;
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}
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unsigned long clk_get_rate(unsigned int clk)
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{
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switch (clk) {
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case core_pll_clk: return pll_freq_get(CORE_PLL);
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case pass_pll_clk: return pll_freq_get(PASS_PLL);
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case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
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case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
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case sys_clk0_1_clk:
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case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
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case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
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case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
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case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
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case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
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case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
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case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
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case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
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case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
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case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
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case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
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case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
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case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
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case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
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case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
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default:
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break;
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}
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return 0;
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}
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