273 lines
7.1 KiB
C
273 lines
7.1 KiB
C
/*
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* Keystone2: pll initialization
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clock_defs.h>
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#define MAX_SPEEDS 13
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static void wait_for_completion(const struct pll_init_data *data)
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{
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int i;
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for (i = 0; i < 100; i++) {
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sdelay(450);
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if ((pllctl_reg_read(data->pll, stat) & PLLSTAT_GO) == 0)
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break;
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}
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}
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void init_pll(const struct pll_init_data *data)
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{
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u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
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pllm = data->pll_m - 1;
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plld = (data->pll_d - 1) & PLL_DIV_MASK;
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pllod = (data->pll_od - 1) & PLL_CLKOD_MASK;
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if (data->pll == MAIN_PLL) {
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/* The requered delay before main PLL configuration */
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sdelay(210000);
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tmp = pllctl_reg_read(data->pll, secctl);
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if (tmp & (PLLCTL_BYPASS)) {
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setbits_le32(keystone_pll_regs[data->pll].reg1,
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BIT(MAIN_ENSAT_OFFSET));
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pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
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PLLCTL_PLLENSRC);
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sdelay(340);
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pllctl_reg_setbits(data->pll, secctl, PLLCTL_BYPASS);
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pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN);
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sdelay(21000);
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pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
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} else {
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pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
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PLLCTL_PLLENSRC);
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sdelay(340);
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}
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pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
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clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
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PLLM_MULT_HI_SMASK, (pllm << 6));
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/* Set the BWADJ (12 bit field) */
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tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
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clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
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PLL_BWADJ_LO_SMASK,
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(tmp_ctl << PLL_BWADJ_LO_SHIFT));
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clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
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PLL_BWADJ_HI_MASK,
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(tmp_ctl >> 8));
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/*
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* Set the pll divider (6 bit field) *
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* PLLD[5:0] is located in MAINPLLCTL0
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*/
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clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
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PLL_DIV_MASK, plld);
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/* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
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pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
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(pllod << PLL_CLKOD_SHIFT));
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wait_for_completion(data);
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pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1);
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pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2);
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pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3);
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pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4);
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pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5);
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pllctl_reg_setbits(data->pll, alnctl, 0x1f);
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/*
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* Set GOSET bit in PLLCMD to initiate the GO operation
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* to change the divide
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*/
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pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GO);
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sdelay(1500); /* wait for the phase adj */
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wait_for_completion(data);
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/* Reset PLL */
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pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
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sdelay(21000); /* Wait for a minimum of 7 us*/
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pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
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sdelay(105000); /* Wait for PLL Lock time (min 50 us) */
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pllctl_reg_clrbits(data->pll, secctl, PLLCTL_BYPASS);
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tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
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#ifndef CONFIG_SOC_K2E
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} else if (data->pll == TETRIS_PLL) {
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bwadj = pllm >> 1;
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/* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
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setbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
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/*
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* Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
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* only applicable for Kepler
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*/
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clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
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/* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
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setbits_le32(keystone_pll_regs[data->pll].reg1 ,
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PLL_PLLRST | PLLCTL_ENSAT);
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/*
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* 3 Program PLLM and PLLD in PLLCTL0 register
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* 4 Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in
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* PLLCTL1 register. BWADJ value must be set
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* to ((PLLM + 1) >> 1) – 1)
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*/
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tmp = ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
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(pllm << 6) |
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(plld & PLL_DIV_MASK) |
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(pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
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__raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
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/* Set BWADJ[11:8] bits */
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tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
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tmp &= ~(PLL_BWADJ_HI_MASK);
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tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
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__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
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/*
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* 5 Wait for at least 5 us based on the reference
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* clock (PLL reset time)
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*/
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sdelay(21000); /* Wait for a minimum of 7 us*/
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/* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
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clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST);
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/*
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* 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
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* (PLL lock time)
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*/
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sdelay(105000);
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/* 8 disable bypass */
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clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
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/*
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* 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
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* only applicable for Kepler
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*/
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setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
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#endif
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} else {
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setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT);
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/*
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* process keeps state of Bypass bit while programming
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* all other DDR PLL settings
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*/
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tmp = __raw_readl(keystone_pll_regs[data->pll].reg0);
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tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */
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/*
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* Set the BWADJ[7:0], PLLD[5:0] and PLLM to PLLCTL0,
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* bypass disabled
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*/
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bwadj = pllm >> 1;
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tmp |= ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
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(pllm << PLL_MULT_SHIFT) |
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(plld & PLL_DIV_MASK) |
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(pllod << PLL_CLKOD_SHIFT);
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__raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
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/* Set BWADJ[11:8] bits */
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tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
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tmp &= ~(PLL_BWADJ_HI_MASK);
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tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
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__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
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/* Reset bit: bit 14 for both DDR3 & PASS PLL */
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tmp = PLL_PLLRST;
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/* Set RESET bit = 1 */
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setbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
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/* Wait for a minimum of 7 us*/
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sdelay(21000);
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/* Clear RESET bit */
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clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
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sdelay(105000);
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/* clear BYPASS (Enable PLL Mode) */
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clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
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sdelay(21000); /* Wait for a minimum of 7 us*/
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}
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/*
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* This is required to provide a delay between multiple
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* consequent PPL configurations
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*/
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sdelay(210000);
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}
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void init_plls(int num_pll, struct pll_init_data *config)
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{
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int i;
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for (i = 0; i < num_pll; i++)
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init_pll(&config[i]);
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}
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static int get_max_speed(u32 val, int *speeds)
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{
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int j;
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if (!val)
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return speeds[0];
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for (j = 1; j < MAX_SPEEDS; j++) {
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if (val == 1)
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return speeds[j];
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val >>= 1;
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}
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return SPD800;
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}
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#ifdef CONFIG_SOC_K2HK
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static u32 read_efuse_bootrom(void)
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{
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return (cpu_revision() > 1) ? __raw_readl(KS2_EFUSE_BOOTROM) :
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__raw_readl(KS2_REV1_DEVSPEED);
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}
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#else
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static inline u32 read_efuse_bootrom(void)
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{
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return __raw_readl(KS2_EFUSE_BOOTROM);
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}
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#endif
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inline int get_max_dev_speed(void)
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{
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return get_max_speed(read_efuse_bootrom() & 0xffff, dev_speeds);
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}
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#ifndef CONFIG_SOC_K2E
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inline int get_max_arm_speed(void)
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{
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return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
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}
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#endif
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void pass_pll_pa_clk_enable(void)
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{
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u32 reg;
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reg = readl(keystone_pll_regs[PASS_PLL].reg1);
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reg |= PLLCTL_PAPLL;
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writel(reg, keystone_pll_regs[PASS_PLL].reg1);
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/* wait till clock is enabled */
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sdelay(15000);
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}
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