213 lines
5.0 KiB
ArmAsm
213 lines
5.0 KiB
ArmAsm
/*
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <version.h>
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/*************************************************************************
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* RESTART
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************************************************************************/
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.text
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.global _start
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_start:
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wrctl status, r0 /* Disable interrupts */
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/* ICACHE INIT -- only the icache line at the reset address
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* is invalidated at reset. So the init must stay within
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* the cache line size (8 words). If GERMS is used, we'll
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* just be invalidating the cache a second time. If cache
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* is not implemented initi behaves as nop.
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*/
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ori r4, r0, %lo(CONFIG_SYS_ICACHELINE_SIZE)
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movhi r5, %hi(CONFIG_SYS_ICACHE_SIZE)
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ori r5, r5, %lo(CONFIG_SYS_ICACHE_SIZE)
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0: initi r5
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sub r5, r5, r4
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bgt r5, r0, 0b
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br _except_end /* Skip the tramp */
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/* EXCEPTION TRAMPOLINE -- the following gets copied
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* to the exception address (below), but is otherwise at the
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* default exception vector offset (0x0020).
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*/
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_except_start:
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movhi et, %hi(_exception)
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ori et, et, %lo(_exception)
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jmp et
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_except_end:
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/* INTERRUPTS -- for now, all interrupts masked and globally
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* disabled.
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*/
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wrctl ienable, r0 /* All disabled */
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/* DCACHE INIT -- if dcache not implemented, initd behaves as
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* nop.
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*/
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movhi r4, %hi(CONFIG_SYS_DCACHELINE_SIZE)
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ori r4, r4, %lo(CONFIG_SYS_DCACHELINE_SIZE)
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movhi r5, %hi(CONFIG_SYS_DCACHE_SIZE)
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ori r5, r5, %lo(CONFIG_SYS_DCACHE_SIZE)
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mov r6, r0
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1: initd 0(r6)
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add r6, r6, r4
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bltu r6, r5, 1b
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/* RELOCATE CODE, DATA & COMMAND TABLE -- the following code
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* assumes code, data and the command table are all
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* contiguous. This lets us relocate everything as a single
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* block. Make sure the linker script matches this ;-)
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*/
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nextpc r4
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_cur: movhi r5, %hi(_cur - _start)
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ori r5, r5, %lo(_cur - _start)
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sub r4, r4, r5 /* r4 <- cur _start */
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mov r8, r4
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movhi r5, %hi(_start)
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ori r5, r5, %lo(_start) /* r5 <- linked _start */
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beq r4, r5, 3f
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movhi r6, %hi(_edata)
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ori r6, r6, %lo(_edata)
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2: ldwio r7, 0(r4)
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addi r4, r4, 4
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stwio r7, 0(r5)
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addi r5, r5, 4
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bne r5, r6, 2b
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3:
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/* ZERO BSS/SBSS -- bss and sbss are assumed to be adjacent
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* and between __bss_start and __bss_end.
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*/
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movhi r5, %hi(__bss_start)
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ori r5, r5, %lo(__bss_start)
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movhi r6, %hi(__bss_end)
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ori r6, r6, %lo(__bss_end)
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beq r5, r6, 5f
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4: stwio r0, 0(r5)
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addi r5, r5, 4
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bne r5, r6, 4b
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5:
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/* JUMP TO RELOC ADDR */
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movhi r4, %hi(_reloc)
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ori r4, r4, %lo(_reloc)
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jmp r4
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_reloc:
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/* COPY EXCEPTION TRAMPOLINE -- copy the tramp to the
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* exception address. Define CONFIG_ROM_STUBS to prevent
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* the copy (e.g. exception in flash or in other
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* softare/firmware component).
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*/
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#if !defined(CONFIG_ROM_STUBS)
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movhi r4, %hi(_except_start)
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ori r4, r4, %lo(_except_start)
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movhi r5, %hi(_except_end)
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ori r5, r5, %lo(_except_end)
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movhi r6, %hi(CONFIG_SYS_EXCEPTION_ADDR)
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ori r6, r6, %lo(CONFIG_SYS_EXCEPTION_ADDR)
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beq r4, r6, 7f /* Skip if at proper addr */
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6: ldwio r7, 0(r4)
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stwio r7, 0(r6)
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addi r4, r4, 4
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addi r6, r6, 4
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bne r4, r5, 6b
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7:
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#endif
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/* STACK INIT -- zero top two words for call back chain.
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*/
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movhi sp, %hi(CONFIG_SYS_INIT_SP)
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ori sp, sp, %lo(CONFIG_SYS_INIT_SP)
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addi sp, sp, -8
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stw r0, 0(sp)
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stw r0, 4(sp)
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mov fp, sp
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/*
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* Call board_init_f -- never returns
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*/
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mov r4, r0
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movhi r2, %hi(board_init_f@h)
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ori r2, r2, %lo(board_init_f@h)
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callr r2
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/* NEVER RETURNS -- but branch to the _start just
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* in case ;-)
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*/
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br _start
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/*
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* relocate_code -- Nios2 handles the relocation above. But
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* the generic board code monkeys with the heap, stack, etc.
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* (it makes some assumptions that may not be appropriate
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* for Nios). Nevertheless, we capitulate here.
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*
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* We'll call the board_init_r from here since this isn't
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* supposed to return.
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*
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* void relocate_code (ulong sp, gd_t *global_data,
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* ulong reloc_addr)
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* __attribute__ ((noreturn));
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*/
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.text
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.global relocate_code
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relocate_code:
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mov sp, r4 /* Set the new sp */
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mov r4, r5
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movhi r8, %hi(board_init_r@h)
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ori r8, r8, %lo(board_init_r@h)
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callr r8
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ret
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/*
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* dly_clks -- Nios2 (like Nios1) doesn't have a timebase in
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* the core. For simple delay loops, we do our best by counting
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* instruction cycles.
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*
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* Instruction performance varies based on the core. For cores
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* with icache and static/dynamic branch prediction (II/f, II/s):
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*
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* Normal ALU (e.g. add, cmp, etc): 1 cycle
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* Branch (correctly predicted, taken): 2 cycles
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* Negative offset is predicted (II/s).
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*
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* For cores without icache and no branch prediction (II/e):
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*
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* Normal ALU (e.g. add, cmp, etc): 6 cycles
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* Branch (no prediction): 6 cycles
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*
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* For simplicity, if an instruction cache is implemented we
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* assume II/f or II/s. Otherwise, we use the II/e.
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*
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*/
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.globl dly_clks
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dly_clks:
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#if (CONFIG_SYS_ICACHE_SIZE > 0)
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subi r4, r4, 3 /* 3 clocks/loop */
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#else
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subi r4, r4, 12 /* 12 clocks/loop */
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#endif
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bge r4, r0, dly_clks
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ret
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.data
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.globl version_string
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version_string:
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.ascii U_BOOT_VERSION_STRING, "\0"
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