Chin Liang See 89a54abf1b ddr: altera: Configuring SDRAM extra cycles timing parameters ... To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>		2016-10-27 08:03:07 +02:00
..
base_addr_a10.h	ARM: socfpga: arria10: add base address map for Arria10	2015-11-30 13:30:19 +01:00
base_addr_ac5.h	ARM: socfpga: rename the cyclone5 and arria5 base address file	2015-11-30 13:30:19 +01:00
clock_manager.h	arm: socfpga: clock: Clean up pll_config.h	2015-08-08 14:14:06 +02:00
fpga_manager.h	…
freeze_controller.h	…
gpio.h	…
nic301.h	…
reset_manager.h	arm: socfpga: Define NAND reset bit	2015-12-22 21:30:02 +01:00
scan_manager.h	arm: socfpga: scan: Add code to get FPGA ID	2015-08-08 14:14:30 +02:00
scu.h	…
sdram.h	ddr: altera: Configuring SDRAM extra cycles timing parameters	2016-10-27 08:03:07 +02:00
system_manager.h	arm: socfpga: fix up a questionable macro for SDMMC	2015-12-20 03:44:56 +01:00
timer.h	…