24 lines
480 B
C
24 lines
480 B
C
/*
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* (C) Copyright 2008,
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* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __SPARC_CACHE_H__
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#define __SPARC_CACHE_H__
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#include <asm/processor.h>
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/*
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* If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise
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* use 32-bytes, the cacheline size for Sparc.
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*/
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#ifdef CONFIG_SYS_CACHELINE_SIZE
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#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
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#else
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#define ARCH_DMA_MINALIGN 32
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#endif
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#endif
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