640 lines
14 KiB
C
640 lines
14 KiB
C
/*
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* Ethernet driver for TI K2HK EVM.
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <console.h>
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#include <net.h>
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#include <phy.h>
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#include <errno.h>
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#include <miiphy.h>
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#include <malloc.h>
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#include <asm/ti-common/keystone_nav.h>
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#include <asm/ti-common/keystone_net.h>
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#include <asm/ti-common/keystone_serdes.h>
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unsigned int emac_open;
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static struct mii_dev *mdio_bus;
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static unsigned int sys_has_mdio = 1;
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#ifdef KEYSTONE2_EMAC_GIG_ENABLE
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#define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
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#else
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#define emac_gigabit_enable(x) /* no gigabit to enable */
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#endif
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#define RX_BUFF_NUMS 24
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#define RX_BUFF_LEN 1520
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#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
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#define SGMII_ANEG_TIMEOUT 4000
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static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
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struct rx_buff_desc net_rx_buffs = {
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.buff_ptr = rx_buffs,
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.num_buffs = RX_BUFF_NUMS,
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.buff_len = RX_BUFF_LEN,
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.rx_flow = 22,
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};
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#ifndef CONFIG_SOC_K2G
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static void keystone2_net_serdes_setup(void);
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#endif
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int keystone2_eth_read_mac_addr(struct eth_device *dev)
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{
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struct eth_priv_t *eth_priv;
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u32 maca = 0;
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u32 macb = 0;
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eth_priv = (struct eth_priv_t *)dev->priv;
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/* Read the e-fuse mac address */
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if (eth_priv->slave_port == 1) {
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maca = __raw_readl(MAC_ID_BASE_ADDR);
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macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
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}
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dev->enetaddr[0] = (macb >> 8) & 0xff;
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dev->enetaddr[1] = (macb >> 0) & 0xff;
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dev->enetaddr[2] = (maca >> 24) & 0xff;
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dev->enetaddr[3] = (maca >> 16) & 0xff;
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dev->enetaddr[4] = (maca >> 8) & 0xff;
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dev->enetaddr[5] = (maca >> 0) & 0xff;
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return 0;
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}
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/* MDIO */
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static int keystone2_mdio_reset(struct mii_dev *bus)
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{
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u_int32_t clkdiv;
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struct mdio_regs *adap_mdio = bus->priv;
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clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
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writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE |
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MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE,
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&adap_mdio->control);
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while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
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;
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return 0;
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}
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/**
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* keystone2_mdio_read - read a PHY register via MDIO interface.
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* Blocks until operation is complete.
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*/
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static int keystone2_mdio_read(struct mii_dev *bus,
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int addr, int devad, int reg)
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{
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int tmp;
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struct mdio_regs *adap_mdio = bus->priv;
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while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
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;
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writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
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((reg & 0x1f) << 21) | ((addr & 0x1f) << 16),
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&adap_mdio->useraccess0);
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/* Wait for command to complete */
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while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
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;
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if (tmp & MDIO_USERACCESS0_ACK)
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return tmp & 0xffff;
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return -1;
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}
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/**
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* keystone2_mdio_write - write to a PHY register via MDIO interface.
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* Blocks until operation is complete.
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*/
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static int keystone2_mdio_write(struct mii_dev *bus,
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int addr, int devad, int reg, u16 val)
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{
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struct mdio_regs *adap_mdio = bus->priv;
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while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
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;
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writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
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((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) |
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(val & 0xffff), &adap_mdio->useraccess0);
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/* Wait for command to complete */
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while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
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;
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return 0;
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}
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static void __attribute__((unused))
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keystone2_eth_gigabit_enable(struct eth_device *dev)
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{
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u_int16_t data;
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struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
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if (sys_has_mdio) {
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data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr,
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MDIO_DEVAD_NONE, 0);
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/* speed selection MSB */
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if (!(data & (1 << 6)))
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return;
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}
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/*
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* Check if link detected is giga-bit
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* If Gigabit mode detected, enable gigbit in MAC
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*/
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writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
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CPGMACSL_REG_CTL) |
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EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
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DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
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}
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#ifdef CONFIG_SOC_K2G
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int keystone_rgmii_config(struct phy_device *phy_dev)
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{
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unsigned int i, status;
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i = 0;
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do {
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if (i > SGMII_ANEG_TIMEOUT) {
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puts(" TIMEOUT !\n");
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phy_dev->link = 0;
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return 0;
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}
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if (ctrlc()) {
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puts("user interrupt!\n");
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phy_dev->link = 0;
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return -EINTR;
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}
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if ((i++ % 500) == 0)
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printf(".");
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udelay(1000); /* 1 ms */
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status = readl(RGMII_STATUS_REG);
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} while (!(status & RGMII_REG_STATUS_LINK));
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puts(" done\n");
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return 0;
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}
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#else
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int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
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{
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unsigned int i, status, mask;
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unsigned int mr_adv_ability, control;
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switch (interface) {
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case SGMII_LINK_MAC_MAC_AUTONEG:
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mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
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SGMII_REG_MR_ADV_LINK |
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SGMII_REG_MR_ADV_FULL_DUPLEX |
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SGMII_REG_MR_ADV_GIG_MODE);
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control = (SGMII_REG_CONTROL_MASTER |
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SGMII_REG_CONTROL_AUTONEG);
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break;
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case SGMII_LINK_MAC_PHY:
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case SGMII_LINK_MAC_PHY_FORCED:
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mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
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control = SGMII_REG_CONTROL_AUTONEG;
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break;
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case SGMII_LINK_MAC_MAC_FORCED:
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mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
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SGMII_REG_MR_ADV_LINK |
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SGMII_REG_MR_ADV_FULL_DUPLEX |
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SGMII_REG_MR_ADV_GIG_MODE);
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control = SGMII_REG_CONTROL_MASTER;
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break;
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case SGMII_LINK_MAC_FIBER:
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mr_adv_ability = 0x20;
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control = SGMII_REG_CONTROL_AUTONEG;
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break;
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default:
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mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
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control = SGMII_REG_CONTROL_AUTONEG;
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}
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__raw_writel(0, SGMII_CTL_REG(port));
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/*
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* Wait for the SerDes pll to lock,
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* but don't trap if lock is never read
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*/
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for (i = 0; i < 1000; i++) {
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udelay(2000);
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status = __raw_readl(SGMII_STATUS_REG(port));
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if ((status & SGMII_REG_STATUS_LOCK) != 0)
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break;
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}
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__raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
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__raw_writel(control, SGMII_CTL_REG(port));
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mask = SGMII_REG_STATUS_LINK;
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if (control & SGMII_REG_CONTROL_AUTONEG)
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mask |= SGMII_REG_STATUS_AUTONEG;
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status = __raw_readl(SGMII_STATUS_REG(port));
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if ((status & mask) == mask)
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return 0;
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printf("\n%s Waiting for SGMII auto negotiation to complete",
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phy_dev->dev->name);
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while ((status & mask) != mask) {
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/*
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* Timeout reached ?
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*/
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if (i > SGMII_ANEG_TIMEOUT) {
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puts(" TIMEOUT !\n");
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phy_dev->link = 0;
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return 0;
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}
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if (ctrlc()) {
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puts("user interrupt!\n");
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phy_dev->link = 0;
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return -EINTR;
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}
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if ((i++ % 500) == 0)
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printf(".");
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udelay(1000); /* 1 ms */
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status = __raw_readl(SGMII_STATUS_REG(port));
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}
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puts(" done\n");
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return 0;
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}
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#endif
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int mac_sl_reset(u32 port)
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{
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u32 i, v;
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if (port >= DEVICE_N_GMACSL_PORTS)
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return GMACSL_RET_INVALID_PORT;
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/* Set the soft reset bit */
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writel(CPGMAC_REG_RESET_VAL_RESET,
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DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
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/* Wait for the bit to clear */
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for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
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v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
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if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
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CPGMAC_REG_RESET_VAL_RESET)
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return GMACSL_RET_OK;
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}
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/* Timeout on the reset */
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return GMACSL_RET_WARN_RESET_INCOMPLETE;
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}
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int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
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{
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u32 v, i;
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int ret = GMACSL_RET_OK;
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if (port >= DEVICE_N_GMACSL_PORTS)
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return GMACSL_RET_INVALID_PORT;
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if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
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cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
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ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
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}
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/* Must wait if the device is undergoing reset */
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for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
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v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
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if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
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CPGMAC_REG_RESET_VAL_RESET)
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break;
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}
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if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
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return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
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writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
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writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
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#ifndef CONFIG_SOC_K2HK
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/* Map RX packet flow priority to 0 */
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writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
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#endif
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return ret;
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}
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int ethss_config(u32 ctl, u32 max_pkt_size)
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{
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u32 i;
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/* Max length register */
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writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
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/* Control register */
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writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
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/* All statistics enabled by default */
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writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
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DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
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/* Reset and enable the ALE */
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writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
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CPSW_REG_VAL_ALE_CTL_BYPASS,
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DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
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/* All ports put into forward mode */
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for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
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writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
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DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
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return 0;
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}
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int ethss_start(void)
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{
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int i;
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struct mac_sl_cfg cfg;
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cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
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cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
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for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
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mac_sl_reset(i);
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mac_sl_config(i, &cfg);
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}
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return 0;
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}
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int ethss_stop(void)
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{
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int i;
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for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
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mac_sl_reset(i);
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return 0;
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}
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int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
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{
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if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
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num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
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return ksnav_send(&netcp_pktdma, buffer,
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num_bytes, (slave_port_num) << 16);
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}
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/* Eth device open */
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static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
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{
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struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
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struct phy_device *phy_dev = eth_priv->phy_dev;
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debug("+ emac_open\n");
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net_rx_buffs.rx_flow = eth_priv->rx_flow;
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sys_has_mdio =
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(eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
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if (sys_has_mdio)
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keystone2_mdio_reset(mdio_bus);
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#ifdef CONFIG_SOC_K2G
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keystone_rgmii_config(phy_dev);
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#else
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keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
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eth_priv->sgmii_link_type);
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#endif
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udelay(10000);
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/* On chip switch configuration */
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ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
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/* TODO: add error handling code */
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if (qm_init()) {
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printf("ERROR: qm_init()\n");
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return -1;
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}
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if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
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qm_close();
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printf("ERROR: netcp_init()\n");
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return -1;
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}
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/*
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* Streaming switch configuration. If not present this
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* statement is defined to void in target.h.
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* If present this is usually defined to a series of register writes
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*/
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hw_config_streaming_switch();
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if (sys_has_mdio) {
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keystone2_mdio_reset(mdio_bus);
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phy_startup(phy_dev);
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if (phy_dev->link == 0) {
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ksnav_close(&netcp_pktdma);
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qm_close();
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return -1;
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}
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}
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emac_gigabit_enable(dev);
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ethss_start();
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debug("- emac_open\n");
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emac_open = 1;
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return 0;
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}
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/* Eth device close */
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void keystone2_eth_close(struct eth_device *dev)
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{
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struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
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struct phy_device *phy_dev = eth_priv->phy_dev;
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debug("+ emac_close\n");
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if (!emac_open)
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return;
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ethss_stop();
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ksnav_close(&netcp_pktdma);
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qm_close();
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phy_shutdown(phy_dev);
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emac_open = 0;
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debug("- emac_close\n");
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}
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/*
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* This function sends a single packet on the network and returns
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* positive number (number of bytes transmitted) or negative for error
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*/
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static int keystone2_eth_send_packet(struct eth_device *dev,
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void *packet, int length)
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{
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int ret_status = -1;
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struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
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struct phy_device *phy_dev = eth_priv->phy_dev;
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genphy_update_link(phy_dev);
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if (phy_dev->link == 0)
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return -1;
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if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
|
|
return ret_status;
|
|
|
|
return length;
|
|
}
|
|
|
|
/*
|
|
* This function handles receipt of a packet from the network
|
|
*/
|
|
static int keystone2_eth_rcv_packet(struct eth_device *dev)
|
|
{
|
|
void *hd;
|
|
int pkt_size;
|
|
u32 *pkt;
|
|
|
|
hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
|
|
if (hd == NULL)
|
|
return 0;
|
|
|
|
net_process_received_packet((uchar *)pkt, pkt_size);
|
|
|
|
ksnav_release_rxhd(&netcp_pktdma, hd);
|
|
|
|
return pkt_size;
|
|
}
|
|
|
|
#ifdef CONFIG_MCAST_TFTP
|
|
static int keystone2_eth_bcast_addr(struct eth_device *dev, u32 ip, u8 set)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* This function initializes the EMAC hardware.
|
|
*/
|
|
int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
|
|
{
|
|
int res;
|
|
struct eth_device *dev;
|
|
struct phy_device *phy_dev;
|
|
|
|
dev = malloc(sizeof(struct eth_device));
|
|
if (dev == NULL)
|
|
return -1;
|
|
|
|
memset(dev, 0, sizeof(struct eth_device));
|
|
|
|
strcpy(dev->name, eth_priv->int_name);
|
|
dev->priv = eth_priv;
|
|
|
|
keystone2_eth_read_mac_addr(dev);
|
|
|
|
dev->iobase = 0;
|
|
dev->init = keystone2_eth_open;
|
|
dev->halt = keystone2_eth_close;
|
|
dev->send = keystone2_eth_send_packet;
|
|
dev->recv = keystone2_eth_rcv_packet;
|
|
#ifdef CONFIG_MCAST_TFTP
|
|
dev->mcast = keystone2_eth_bcast_addr;
|
|
#endif
|
|
|
|
eth_register(dev);
|
|
|
|
/* Register MDIO bus if it's not registered yet */
|
|
if (!mdio_bus) {
|
|
mdio_bus = mdio_alloc();
|
|
mdio_bus->read = keystone2_mdio_read;
|
|
mdio_bus->write = keystone2_mdio_write;
|
|
mdio_bus->reset = keystone2_mdio_reset;
|
|
mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR;
|
|
strcpy(mdio_bus->name, "ethernet-mdio");
|
|
|
|
res = mdio_register(mdio_bus);
|
|
if (res)
|
|
return res;
|
|
}
|
|
|
|
#ifndef CONFIG_SOC_K2G
|
|
keystone2_net_serdes_setup();
|
|
#endif
|
|
|
|
/* Create phy device and bind it with driver */
|
|
#ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
|
|
phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr,
|
|
dev, eth_priv->phy_if);
|
|
phy_config(phy_dev);
|
|
#else
|
|
phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr,
|
|
eth_priv->phy_if);
|
|
phy_dev->dev = dev;
|
|
#endif
|
|
eth_priv->phy_dev = phy_dev;
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
|
|
.clk = SERDES_CLOCK_156P25M,
|
|
.rate = SERDES_RATE_5G,
|
|
.rate_mode = SERDES_QUARTER_RATE,
|
|
.intf = SERDES_PHY_SGMII,
|
|
.loopback = 0,
|
|
};
|
|
|
|
#ifndef CONFIG_SOC_K2G
|
|
static void keystone2_net_serdes_setup(void)
|
|
{
|
|
ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
|
|
&ks2_serdes_sgmii_156p25mhz,
|
|
CONFIG_KSNET_SERDES_LANES_PER_SGMII);
|
|
|
|
#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
|
|
ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
|
|
&ks2_serdes_sgmii_156p25mhz,
|
|
CONFIG_KSNET_SERDES_LANES_PER_SGMII);
|
|
#endif
|
|
|
|
/* wait till setup */
|
|
udelay(5000);
|
|
}
|
|
#endif
|