383 lines
10 KiB
C
383 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* drivers/i2c/rcar_i2c.c
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*
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* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
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*
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* Clock configuration based on Linux i2c-rcar.c:
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* Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
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* Copyright (C) 2011-2015 Renesas Electronics Corporation
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* Copyright (C) 2012-14 Renesas Solutions Corp.
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* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <wait_bit.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#define RCAR_I2C_ICSCR 0x00 /* slave ctrl */
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#define RCAR_I2C_ICMCR 0x04 /* master ctrl */
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#define RCAR_I2C_ICMCR_MDBS BIT(7) /* non-fifo mode switch */
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#define RCAR_I2C_ICMCR_FSCL BIT(6) /* override SCL pin */
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#define RCAR_I2C_ICMCR_FSDA BIT(5) /* override SDA pin */
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#define RCAR_I2C_ICMCR_OBPC BIT(4) /* override pins */
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#define RCAR_I2C_ICMCR_MIE BIT(3) /* master if enable */
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#define RCAR_I2C_ICMCR_TSBE BIT(2)
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#define RCAR_I2C_ICMCR_FSB BIT(1) /* force stop bit */
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#define RCAR_I2C_ICMCR_ESG BIT(0) /* enable start bit gen */
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#define RCAR_I2C_ICSSR 0x08 /* slave status */
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#define RCAR_I2C_ICMSR 0x0c /* master status */
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#define RCAR_I2C_ICMSR_MASK 0x7f
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#define RCAR_I2C_ICMSR_MNR BIT(6) /* Nack */
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#define RCAR_I2C_ICMSR_MAL BIT(5) /* Arbitration lost */
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#define RCAR_I2C_ICMSR_MST BIT(4) /* Stop */
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#define RCAR_I2C_ICMSR_MDE BIT(3)
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#define RCAR_I2C_ICMSR_MDT BIT(2)
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#define RCAR_I2C_ICMSR_MDR BIT(1)
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#define RCAR_I2C_ICMSR_MAT BIT(0)
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#define RCAR_I2C_ICSIER 0x10 /* slave irq enable */
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#define RCAR_I2C_ICMIER 0x14 /* master irq enable */
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#define RCAR_I2C_ICCCR 0x18 /* clock dividers */
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#define RCAR_I2C_ICCCR_SCGD_OFF 3
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#define RCAR_I2C_ICSAR 0x1c /* slave address */
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#define RCAR_I2C_ICMAR 0x20 /* master address */
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#define RCAR_I2C_ICRXD_ICTXD 0x24 /* data port */
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/*
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* First Bit Setup Cycle (Gen3).
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* Defines 1st bit delay between SDA and SCL.
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*/
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#define RCAR_I2C_ICFBSCR 0x38
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#define RCAR_I2C_ICFBSCR_TCYC17 0x0f /* 17*Tcyc */
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enum rcar_i2c_type {
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RCAR_I2C_TYPE_GEN2,
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RCAR_I2C_TYPE_GEN3,
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};
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struct rcar_i2c_priv {
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void __iomem *base;
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struct clk clk;
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u32 fall_ns;
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u32 rise_ns;
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u32 intdelay;
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u32 icccr;
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enum rcar_i2c_type type;
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};
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static int rcar_i2c_finish(struct udevice *dev)
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{
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struct rcar_i2c_priv *priv = dev_get_priv(dev);
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int ret;
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ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, RCAR_I2C_ICMSR_MST,
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true, 10, true);
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writel(0, priv->base + RCAR_I2C_ICSSR);
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writel(0, priv->base + RCAR_I2C_ICMSR);
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writel(0, priv->base + RCAR_I2C_ICMCR);
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return ret;
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}
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static int rcar_i2c_recover(struct udevice *dev)
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{
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struct rcar_i2c_priv *priv = dev_get_priv(dev);
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u32 mcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_OBPC;
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u32 mcra = mcr | RCAR_I2C_ICMCR_FSDA;
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int i;
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u32 mstat;
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/* Send 9 SCL pulses */
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for (i = 0; i < 9; i++) {
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writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
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udelay(5);
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writel(mcra, priv->base + RCAR_I2C_ICMCR);
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udelay(5);
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}
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/* Send stop condition */
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udelay(5);
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writel(mcra, priv->base + RCAR_I2C_ICMCR);
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udelay(5);
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writel(mcr, priv->base + RCAR_I2C_ICMCR);
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udelay(5);
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writel(mcr | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
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udelay(5);
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writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
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udelay(5);
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mstat = readl(priv->base + RCAR_I2C_ICMSR);
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return mstat & RCAR_I2C_ICMCR_FSDA ? -EBUSY : 0;
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}
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static int rcar_i2c_set_addr(struct udevice *dev, u8 chip, u8 read)
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{
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struct rcar_i2c_priv *priv = dev_get_priv(dev);
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u32 mask = RCAR_I2C_ICMSR_MAT |
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(read ? RCAR_I2C_ICMSR_MDR : RCAR_I2C_ICMSR_MDE);
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int ret;
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writel(0, priv->base + RCAR_I2C_ICMIER);
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writel(RCAR_I2C_ICMCR_MDBS, priv->base + RCAR_I2C_ICMCR);
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writel(0, priv->base + RCAR_I2C_ICMSR);
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writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
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/* Wait for the bus */
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ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMCR,
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RCAR_I2C_ICMCR_FSDA, false, 2, true);
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if (ret) {
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if (rcar_i2c_recover(dev)) {
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dev_err(dev, "Bus busy, aborting\n");
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return ret;
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}
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}
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writel((chip << 1) | read, priv->base + RCAR_I2C_ICMAR);
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/* Reset */
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writel(RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE | RCAR_I2C_ICMCR_ESG,
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priv->base + RCAR_I2C_ICMCR);
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/* Clear Status */
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writel(0, priv->base + RCAR_I2C_ICMSR);
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ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, mask,
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true, 100, true);
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if (ret)
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return ret;
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/* Check NAK */
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if (readl(priv->base + RCAR_I2C_ICMSR) & RCAR_I2C_ICMSR_MNR)
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return -EREMOTEIO;
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return 0;
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}
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static int rcar_i2c_read_common(struct udevice *dev, struct i2c_msg *msg)
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{
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struct rcar_i2c_priv *priv = dev_get_priv(dev);
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u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
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int i, ret = -EREMOTEIO;
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for (i = 0; i < msg->len; i++) {
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if (msg->len - 1 == i)
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icmcr |= RCAR_I2C_ICMCR_FSB;
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writel(icmcr, priv->base + RCAR_I2C_ICMCR);
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writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
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ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
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RCAR_I2C_ICMSR_MDR, true, 100, true);
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if (ret)
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return ret;
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msg->buf[i] = readl(priv->base + RCAR_I2C_ICRXD_ICTXD) & 0xff;
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}
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writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
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return rcar_i2c_finish(dev);
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}
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static int rcar_i2c_write_common(struct udevice *dev, struct i2c_msg *msg)
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{
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struct rcar_i2c_priv *priv = dev_get_priv(dev);
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u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
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int i, ret = -EREMOTEIO;
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for (i = 0; i < msg->len; i++) {
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writel(msg->buf[i], priv->base + RCAR_I2C_ICRXD_ICTXD);
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writel(icmcr, priv->base + RCAR_I2C_ICMCR);
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writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
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ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
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RCAR_I2C_ICMSR_MDE, true, 100, true);
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if (ret)
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return ret;
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}
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writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
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icmcr |= RCAR_I2C_ICMCR_FSB;
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writel(icmcr, priv->base + RCAR_I2C_ICMCR);
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return rcar_i2c_finish(dev);
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}
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static int rcar_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
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{
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int ret;
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for (; nmsgs > 0; nmsgs--, msg++) {
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ret = rcar_i2c_set_addr(dev, msg->addr, !!(msg->flags & I2C_M_RD));
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if (ret)
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return ret;
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if (msg->flags & I2C_M_RD)
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ret = rcar_i2c_read_common(dev, msg);
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else
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ret = rcar_i2c_write_common(dev, msg);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int rcar_i2c_probe_chip(struct udevice *dev, uint addr, uint flags)
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{
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struct rcar_i2c_priv *priv = dev_get_priv(dev);
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int ret;
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/* Ignore address 0, slave address */
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if (addr == 0)
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return -EINVAL;
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ret = rcar_i2c_set_addr(dev, addr, 1);
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writel(0, priv->base + RCAR_I2C_ICMSR);
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return ret;
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}
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static int rcar_i2c_set_speed(struct udevice *dev, uint bus_freq_hz)
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{
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struct rcar_i2c_priv *priv = dev_get_priv(dev);
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u32 scgd, cdf, round, ick, sum, scl;
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unsigned long rate;
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/*
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* calculate SCL clock
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* see
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* ICCCR
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*
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* ick = clkp / (1 + CDF)
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* SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
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*
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* ick : I2C internal clock < 20 MHz
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* ticf : I2C SCL falling time
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* tr : I2C SCL rising time
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* intd : LSI internal delay
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* clkp : peripheral_clk
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* F[] : integer up-valuation
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*/
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rate = clk_get_rate(&priv->clk);
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cdf = rate / 20000000;
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if (cdf >= 8) {
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dev_err(dev, "Input clock %lu too high\n", rate);
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return -EIO;
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}
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ick = rate / (cdf + 1);
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/*
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* it is impossible to calculate large scale
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* number on u32. separate it
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*
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* F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
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* = F[sum * ick / 1000000000]
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* = F[(ick / 1000000) * sum / 1000]
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*/
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sum = priv->fall_ns + priv->rise_ns + priv->intdelay;
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round = (ick + 500000) / 1000000 * sum;
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round = (round + 500) / 1000;
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/*
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* SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
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*
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* Calculation result (= SCL) should be less than
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* bus_speed for hardware safety
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*
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* We could use something along the lines of
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* div = ick / (bus_speed + 1) + 1;
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* scgd = (div - 20 - round + 7) / 8;
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* scl = ick / (20 + (scgd * 8) + round);
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* (not fully verified) but that would get pretty involved
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*/
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for (scgd = 0; scgd < 0x40; scgd++) {
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scl = ick / (20 + (scgd * 8) + round);
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if (scl <= bus_freq_hz)
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goto scgd_find;
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}
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dev_err(dev, "it is impossible to calculate best SCL\n");
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return -EIO;
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scgd_find:
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dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
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scl, bus_freq_hz, clk_get_rate(&priv->clk), round, cdf, scgd);
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priv->icccr = (scgd << RCAR_I2C_ICCCR_SCGD_OFF) | cdf;
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writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
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if (priv->type == RCAR_I2C_TYPE_GEN3) {
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/* Set SCL/SDA delay */
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writel(RCAR_I2C_ICFBSCR_TCYC17, priv->base + RCAR_I2C_ICFBSCR);
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}
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return 0;
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}
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static int rcar_i2c_probe(struct udevice *dev)
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{
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struct rcar_i2c_priv *priv = dev_get_priv(dev);
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int ret;
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priv->base = dev_read_addr_ptr(dev);
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priv->rise_ns = dev_read_u32_default(dev,
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"i2c-scl-rising-time-ns", 200);
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priv->fall_ns = dev_read_u32_default(dev,
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"i2c-scl-falling-time-ns", 35);
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priv->intdelay = dev_read_u32_default(dev,
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"i2c-scl-internal-delay-ns", 5);
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priv->type = dev_get_driver_data(dev);
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret)
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return ret;
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ret = clk_enable(&priv->clk);
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if (ret)
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return ret;
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/* reset slave mode */
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writel(0, priv->base + RCAR_I2C_ICSIER);
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writel(0, priv->base + RCAR_I2C_ICSAR);
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writel(0, priv->base + RCAR_I2C_ICSCR);
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writel(0, priv->base + RCAR_I2C_ICSSR);
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/* reset master mode */
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writel(0, priv->base + RCAR_I2C_ICMIER);
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writel(0, priv->base + RCAR_I2C_ICMCR);
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writel(0, priv->base + RCAR_I2C_ICMSR);
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writel(0, priv->base + RCAR_I2C_ICMAR);
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ret = rcar_i2c_set_speed(dev, I2C_SPEED_STANDARD_RATE);
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if (ret)
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clk_disable(&priv->clk);
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return ret;
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}
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static const struct dm_i2c_ops rcar_i2c_ops = {
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.xfer = rcar_i2c_xfer,
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.probe_chip = rcar_i2c_probe_chip,
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.set_bus_speed = rcar_i2c_set_speed,
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};
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static const struct udevice_id rcar_i2c_ids[] = {
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{ .compatible = "renesas,rcar-gen2-i2c", .data = RCAR_I2C_TYPE_GEN2 },
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{ .compatible = "renesas,rcar-gen3-i2c", .data = RCAR_I2C_TYPE_GEN3 },
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{ }
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};
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U_BOOT_DRIVER(i2c_rcar) = {
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.name = "i2c_rcar",
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.id = UCLASS_I2C,
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.of_match = rcar_i2c_ids,
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.probe = rcar_i2c_probe,
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.priv_auto = sizeof(struct rcar_i2c_priv),
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.ops = &rcar_i2c_ops,
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};
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