512 lines
12 KiB
C
512 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* TI QSPI driver
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*
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* Copyright (C) 2013, Texas Instruments, Incorporated
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <log.h>
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#include <asm/cache.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/omap.h>
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#include <malloc.h>
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#include <spi.h>
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#include <spi-mem.h>
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#include <dm.h>
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#include <asm/gpio.h>
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#include <asm/omap_gpio.h>
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#include <asm/omap_common.h>
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#include <asm/ti-common/ti-edma3.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <regmap.h>
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#include <syscon.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ti qpsi register bit masks */
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#define QSPI_TIMEOUT 2000000
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#define QSPI_FCLK 192000000
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#define QSPI_DRA7XX_FCLK 76800000
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#define QSPI_WLEN_MAX_BITS 128
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#define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3)
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#define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
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/* clock control */
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#define QSPI_CLK_EN BIT(31)
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#define QSPI_CLK_DIV_MAX 0xffff
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/* command */
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#define QSPI_EN_CS(n) (n << 28)
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#define QSPI_WLEN(n) ((n-1) << 19)
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#define QSPI_3_PIN BIT(18)
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#define QSPI_RD_SNGL BIT(16)
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#define QSPI_WR_SNGL (2 << 16)
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#define QSPI_INVAL (4 << 16)
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#define QSPI_RD_QUAD (7 << 16)
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/* device control */
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#define QSPI_CKPHA(n) (1 << (2 + n*8))
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#define QSPI_CSPOL(n) (1 << (1 + n*8))
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#define QSPI_CKPOL(n) (1 << (n*8))
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/* status */
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#define QSPI_WC BIT(1)
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#define QSPI_BUSY BIT(0)
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#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
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#define QSPI_XFER_DONE QSPI_WC
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#define MM_SWITCH 0x01
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#define MEM_CS(cs) ((cs + 1) << 8)
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#define MEM_CS_UNSELECT 0xfffff8ff
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#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
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#define QSPI_SETUP0_READ_DUAL (0x1 << 12)
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#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
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#define QSPI_SETUP0_ADDR_SHIFT (8)
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#define QSPI_SETUP0_DBITS_SHIFT (10)
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#define TI_QSPI_SETUP_REG(priv, cs) (&(priv)->base->setup0 + (cs))
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/* ti qspi register set */
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struct ti_qspi_regs {
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u32 pid;
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u32 pad0[3];
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u32 sysconfig;
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u32 pad1[3];
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u32 int_stat_raw;
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u32 int_stat_en;
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u32 int_en_set;
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u32 int_en_ctlr;
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u32 intc_eoi;
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u32 pad2[3];
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u32 clk_ctrl;
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u32 dc;
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u32 cmd;
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u32 status;
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u32 data;
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u32 setup0;
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u32 setup1;
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u32 setup2;
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u32 setup3;
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u32 memswitch;
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u32 data1;
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u32 data2;
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u32 data3;
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};
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/* ti qspi priv */
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struct ti_qspi_priv {
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void *memory_map;
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size_t mmap_size;
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uint max_hz;
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u32 num_cs;
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struct ti_qspi_regs *base;
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void *ctrl_mod_mmap;
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ulong fclk;
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unsigned int mode;
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u32 cmd;
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u32 dc;
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};
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static int ti_qspi_set_speed(struct udevice *bus, uint hz)
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{
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struct ti_qspi_priv *priv = dev_get_priv(bus);
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uint clk_div;
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if (!hz)
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clk_div = 0;
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else
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clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
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/* truncate clk_div value to QSPI_CLK_DIV_MAX */
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if (clk_div > QSPI_CLK_DIV_MAX)
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clk_div = QSPI_CLK_DIV_MAX;
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debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
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/* disable SCLK */
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writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
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&priv->base->clk_ctrl);
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/* enable SCLK and program the clk divider */
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writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
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return 0;
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}
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static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
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{
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writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
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/* dummy readl to ensure bus sync */
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readl(&priv->base->cmd);
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}
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static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
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{
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u32 val;
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val = readl(ctrl_mod_mmap);
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if (enable)
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val |= MEM_CS(cs);
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else
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val &= MEM_CS_UNSELECT;
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writel(val, ctrl_mod_mmap);
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}
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static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct dm_spi_slave_plat *slave = dev_get_parent_plat(dev);
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struct ti_qspi_priv *priv;
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struct udevice *bus;
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uint words = bitlen >> 3; /* fixed 8-bit word length */
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const uchar *txp = dout;
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uchar *rxp = din;
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uint status;
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int timeout;
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unsigned int cs = slave->cs;
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bus = dev->parent;
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priv = dev_get_priv(bus);
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if (cs > priv->num_cs) {
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debug("invalid qspi chip select\n");
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return -EINVAL;
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}
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if (bitlen == 0)
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return -1;
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if (bitlen % 8) {
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debug("spi_xfer: Non byte aligned SPI transfer\n");
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return -1;
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}
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/* Setup command reg */
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priv->cmd = 0;
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priv->cmd |= QSPI_WLEN(8);
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priv->cmd |= QSPI_EN_CS(cs);
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if (priv->mode & SPI_3WIRE)
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priv->cmd |= QSPI_3_PIN;
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priv->cmd |= 0xfff;
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while (words) {
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u8 xfer_len = 0;
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if (txp) {
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u32 cmd = priv->cmd;
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if (words >= QSPI_WLEN_MAX_BYTES) {
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u32 *txbuf = (u32 *)txp;
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u32 data;
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data = cpu_to_be32(*txbuf++);
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writel(data, &priv->base->data3);
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data = cpu_to_be32(*txbuf++);
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writel(data, &priv->base->data2);
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data = cpu_to_be32(*txbuf++);
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writel(data, &priv->base->data1);
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data = cpu_to_be32(*txbuf++);
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writel(data, &priv->base->data);
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cmd &= ~QSPI_WLEN_MASK;
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cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
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xfer_len = QSPI_WLEN_MAX_BYTES;
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} else {
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writeb(*txp, &priv->base->data);
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xfer_len = 1;
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}
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debug("tx cmd %08x dc %08x\n",
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cmd | QSPI_WR_SNGL, priv->dc);
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writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
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status = readl(&priv->base->status);
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timeout = QSPI_TIMEOUT;
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while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
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if (--timeout < 0) {
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printf("spi_xfer: TX timeout!\n");
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return -1;
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}
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status = readl(&priv->base->status);
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}
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txp += xfer_len;
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debug("tx done, status %08x\n", status);
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}
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if (rxp) {
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debug("rx cmd %08x dc %08x\n",
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((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
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writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
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status = readl(&priv->base->status);
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timeout = QSPI_TIMEOUT;
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while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
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if (--timeout < 0) {
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printf("spi_xfer: RX timeout!\n");
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return -1;
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}
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status = readl(&priv->base->status);
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}
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*rxp++ = readl(&priv->base->data);
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xfer_len = 1;
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debug("rx done, status %08x, read %02x\n",
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status, *(rxp-1));
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}
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words -= xfer_len;
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}
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/* Terminate frame */
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if (flags & SPI_XFER_END)
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ti_qspi_cs_deactivate(priv);
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return 0;
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}
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/* TODO: control from sf layer to here through dm-spi */
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static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
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{
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#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
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unsigned int addr = (unsigned int) (data);
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unsigned int edma_slot_num = 1;
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/* Invalidate the area, so no writeback into the RAM races with DMA */
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invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
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/* enable edma3 clocks */
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enable_edma3_clocks();
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/* Call edma3 api to do actual DMA transfer */
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edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
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/* disable edma3 clocks */
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disable_edma3_clocks();
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#else
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memcpy_fromio(data, offset, len);
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#endif
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*((unsigned int *)offset) += len;
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}
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static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, int cs,
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u8 opcode, u8 data_nbits, u8 addr_width,
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u8 dummy_bytes)
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{
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u32 memval = opcode;
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switch (data_nbits) {
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case 4:
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memval |= QSPI_SETUP0_READ_QUAD;
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break;
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case 2:
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memval |= QSPI_SETUP0_READ_DUAL;
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break;
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default:
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memval |= QSPI_SETUP0_READ_NORMAL;
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break;
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}
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memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
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dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
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writel(memval, TI_QSPI_SETUP_REG(priv, cs));
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}
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static int ti_qspi_set_mode(struct udevice *bus, uint mode)
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{
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struct ti_qspi_priv *priv = dev_get_priv(bus);
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priv->dc = 0;
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if (mode & SPI_CPHA)
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priv->dc |= QSPI_CKPHA(0);
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if (mode & SPI_CPOL)
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priv->dc |= QSPI_CKPOL(0);
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if (mode & SPI_CS_HIGH)
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priv->dc |= QSPI_CSPOL(0);
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return 0;
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}
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static int ti_qspi_exec_mem_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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struct dm_spi_slave_plat *slave_plat;
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struct ti_qspi_priv *priv;
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struct udevice *bus;
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u32 from = 0;
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int ret = 0;
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bus = slave->dev->parent;
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priv = dev_get_priv(bus);
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slave_plat = dev_get_parent_plat(slave->dev);
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/* Only optimize read path. */
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if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
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!op->addr.nbytes || op->addr.nbytes > 4)
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return -ENOTSUPP;
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/* Address exceeds MMIO window size, fall back to regular mode. */
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from = op->addr.val;
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if (from + op->data.nbytes > priv->mmap_size)
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return -ENOTSUPP;
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ti_qspi_setup_mmap_read(priv, slave_plat->cs, op->cmd.opcode,
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op->data.buswidth, op->addr.nbytes,
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op->dummy.nbytes);
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ti_qspi_copy_mmap((void *)op->data.buf.in,
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(void *)priv->memory_map + from, op->data.nbytes);
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return ret;
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}
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static int ti_qspi_claim_bus(struct udevice *dev)
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{
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struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
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struct ti_qspi_priv *priv;
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struct udevice *bus;
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bus = dev->parent;
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priv = dev_get_priv(bus);
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if (slave_plat->cs > priv->num_cs) {
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debug("invalid qspi chip select\n");
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return -EINVAL;
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}
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writel(MM_SWITCH, &priv->base->memswitch);
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if (priv->ctrl_mod_mmap)
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ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
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slave_plat->cs, true);
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writel(priv->dc, &priv->base->dc);
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writel(0, &priv->base->cmd);
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writel(0, &priv->base->data);
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priv->dc <<= slave_plat->cs * 8;
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writel(priv->dc, &priv->base->dc);
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return 0;
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}
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static int ti_qspi_release_bus(struct udevice *dev)
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{
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struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
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struct ti_qspi_priv *priv;
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struct udevice *bus;
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bus = dev->parent;
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priv = dev_get_priv(bus);
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writel(~MM_SWITCH, &priv->base->memswitch);
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if (priv->ctrl_mod_mmap)
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ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
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slave_plat->cs, false);
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writel(0, &priv->base->dc);
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writel(0, &priv->base->cmd);
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writel(0, &priv->base->data);
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writel(0, TI_QSPI_SETUP_REG(priv, slave_plat->cs));
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return 0;
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}
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static int ti_qspi_probe(struct udevice *bus)
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{
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struct ti_qspi_priv *priv = dev_get_priv(bus);
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priv->fclk = dev_get_driver_data(bus);
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return 0;
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}
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static void *map_syscon_chipselects(struct udevice *bus)
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{
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#if CONFIG_IS_ENABLED(SYSCON)
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struct udevice *syscon;
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struct regmap *regmap;
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const fdt32_t *cell;
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int len, err;
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err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
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"syscon-chipselects", &syscon);
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if (err) {
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debug("%s: unable to find syscon device (%d)\n", __func__,
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err);
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return NULL;
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}
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regmap = syscon_get_regmap(syscon);
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if (IS_ERR(regmap)) {
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debug("%s: unable to find regmap (%ld)\n", __func__,
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PTR_ERR(regmap));
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return NULL;
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}
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cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
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"syscon-chipselects", &len);
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if (len < 2*sizeof(fdt32_t)) {
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debug("%s: offset not available\n", __func__);
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return NULL;
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}
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return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
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#else
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fdt_addr_t addr;
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addr = devfdt_get_addr_index(bus, 2);
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return (addr == FDT_ADDR_T_NONE) ? NULL :
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map_physmem(addr, 0, MAP_NOCACHE);
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#endif
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}
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static int ti_qspi_of_to_plat(struct udevice *bus)
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{
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struct ti_qspi_priv *priv = dev_get_priv(bus);
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const void *blob = gd->fdt_blob;
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int node = dev_of_offset(bus);
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fdt_addr_t mmap_addr;
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fdt_addr_t mmap_size;
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priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
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priv->base = map_physmem(dev_read_addr(bus),
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sizeof(struct ti_qspi_regs), MAP_NOCACHE);
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mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
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priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
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priv->mmap_size = mmap_size;
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priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0);
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if (!priv->max_hz) {
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debug("Error: Max frequency missing\n");
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return -ENODEV;
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}
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priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
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debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
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(int)priv->base, priv->max_hz);
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return 0;
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}
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static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
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.exec_op = ti_qspi_exec_mem_op,
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};
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static const struct dm_spi_ops ti_qspi_ops = {
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.claim_bus = ti_qspi_claim_bus,
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.release_bus = ti_qspi_release_bus,
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.xfer = ti_qspi_xfer,
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.set_speed = ti_qspi_set_speed,
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.set_mode = ti_qspi_set_mode,
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.mem_ops = &ti_qspi_mem_ops,
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};
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static const struct udevice_id ti_qspi_ids[] = {
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{ .compatible = "ti,dra7xxx-qspi", .data = QSPI_DRA7XX_FCLK},
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{ .compatible = "ti,am4372-qspi", .data = QSPI_FCLK},
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{ }
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};
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U_BOOT_DRIVER(ti_qspi) = {
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.name = "ti_qspi",
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.id = UCLASS_SPI,
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.of_match = ti_qspi_ids,
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.ops = &ti_qspi_ops,
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.of_to_plat = ti_qspi_of_to_plat,
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.priv_auto = sizeof(struct ti_qspi_priv),
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.probe = ti_qspi_probe,
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};
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