115 lines
2.4 KiB
C
115 lines
2.4 KiB
C
/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __FSL_SERDES_H
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#define __FSL_SERDES_H
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#include <config.h>
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enum srds_prtcl {
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NONE = 0,
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PCIE1,
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PCIE2,
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PCIE3,
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PCIE4,
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SATA1,
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SATA2,
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SRIO1,
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SRIO2,
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SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3,
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SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5,
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SGMII_FM1_DTSEC6,
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SGMII_FM1_DTSEC9,
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SGMII_FM1_DTSEC10,
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SGMII_FM2_DTSEC1,
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SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3,
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SGMII_FM2_DTSEC4,
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SGMII_FM2_DTSEC5,
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SGMII_FM2_DTSEC6,
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SGMII_FM2_DTSEC9,
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SGMII_FM2_DTSEC10,
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SGMII_TSEC1,
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SGMII_TSEC2,
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SGMII_TSEC3,
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SGMII_TSEC4,
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XAUI_FM1,
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XAUI_FM2,
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AURORA,
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CPRI1,
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CPRI2,
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CPRI3,
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CPRI4,
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CPRI5,
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CPRI6,
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CPRI7,
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CPRI8,
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XAUI_FM1_MAC9,
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XAUI_FM1_MAC10,
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XAUI_FM2_MAC9,
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XAUI_FM2_MAC10,
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HIGIG_FM1_MAC9,
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HIGIG_FM1_MAC10,
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HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC10,
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QSGMII_FM1_A, /* A indicates MACs 1-4 */
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QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
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QSGMII_FM2_A,
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QSGMII_FM2_B,
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XFI_FM1_MAC9,
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XFI_FM1_MAC10,
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XFI_FM2_MAC9,
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XFI_FM2_MAC10,
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INTERLAKEN,
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SGMII_SW1_DTSEC1, /* SW indicates on L2 switch */
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SGMII_SW1_DTSEC2,
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SGMII_SW1_DTSEC3,
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SGMII_SW1_DTSEC4,
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SGMII_SW1_DTSEC5,
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SGMII_SW1_DTSEC6,
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QSGMII_SW1_A, /* SW indicates on L2 swtich */
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QSGMII_SW1_B,
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};
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enum srds {
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FSL_SRDS_1 = 0,
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FSL_SRDS_2 = 1,
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FSL_SRDS_3 = 2,
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FSL_SRDS_4 = 3,
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};
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int is_serdes_configured(enum srds_prtcl device);
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void fsl_serdes_init(void);
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#ifdef CONFIG_FSL_CORENET
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
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#else
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int serdes_get_first_lane(enum srds_prtcl device);
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#endif
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
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void serdes_reset_rx(enum srds_prtcl device);
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#endif
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#endif
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#endif /* __FSL_SERDES_H */
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