70 lines
1.2 KiB
Plaintext
70 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018-2021 Marvell International Ltd.
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*/
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#include "cn9130-db-B.dts"
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#include "cn9131-db.dtsi"
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/ {
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model = "Marvell CN9131 development board (CP NAND) setup(B)";
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compatible = "marvell,cn9131-db", "marvell,armada-ap806-quad",
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"marvell,armada-ap806";
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};
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&cp1_comphy {
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/* Serdes Configuration:
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* Lane 0: PCIe0 (x2)
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* Lane 1: PCIe0 (x2)
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* Lane 2: SFI (port 0)
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* Lane 3: USB1
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* Lane 4: SGMII (port 1)
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* Lane 5: SATA1
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*/
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phy0 {
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phy-type = <COMPHY_TYPE_PEX0>;
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};
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phy1 {
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phy-type = <COMPHY_TYPE_PEX0>;
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};
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phy2 {
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phy-type = <COMPHY_TYPE_SFI0>;
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phy-speed = <COMPHY_SPEED_10_3125G>;
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};
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phy3 {
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phy-type = <COMPHY_TYPE_USB3_HOST1>;
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};
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phy4 {
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phy-type = <COMPHY_TYPE_SGMII1>;
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phy-speed = <COMPHY_SPEED_1_25G>;
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};
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phy5 {
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phy-type = <COMPHY_TYPE_SATA1>;
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};
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};
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&cp1_ethernet {
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status = "okay";
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};
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/* 3310 RJ45 CON55 */
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&cp1_eth0 {
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status = "okay";
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phy-mode = "sfi"; /* lane-2 */
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phy = <&sfi_phy8>; /* required by 3310 fw download */
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};
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/* CON50 */
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&cp1_eth1 {
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status = "okay";
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phy-mode = "sgmii"; /* lane-4 */
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marvell,sfp-tx-disable-gpio = <&cp1_gpio0 9 GPIO_ACTIVE_HIGH>;
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};
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&cp1_xmdio {
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status = "okay";
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sfi_phy8: ethernet-phy@8 {
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reg = <8>;
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};
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};
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