305 lines
6.0 KiB
Plaintext
305 lines
6.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* Copyright 2015 Timesys Corporation.
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* Copyright 2015 General Electric Company
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "imx6q-bx50v3.dtsi"
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/ {
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model = "General Electric B850v3";
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compatible = "ge,imx6q-b850v3", "advantech,imx6q-ba16", "fsl,imx6q";
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chosen {
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stdout-path = &uart3;
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};
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};
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&clks {
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assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
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<&clks IMX6QDL_CLK_LDB_DI1_SEL>,
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<&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
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<&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
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assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
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<&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
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<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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<&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
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};
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&ldb {
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fsl,dual-channel;
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status = "okay";
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lvds0: lvds-channel@0 {
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fsl,data-mapping = "spwg";
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fsl,data-width = <24>;
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status = "okay";
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port@4 {
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reg = <4>;
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lvds0_out: endpoint {
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remote-endpoint = <&stdp4028_in>;
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};
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};
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};
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};
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&i2c2 {
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pca9547_ddc: mux@70 {
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compatible = "nxp,pca9547";
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reg = <0x70>;
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#address-cells = <1>;
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#size-cells = <0>;
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mux2_i2c1: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0>;
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};
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mux2_i2c2: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1>;
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};
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mux2_i2c3: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2>;
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};
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mux2_i2c4: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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};
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mux2_i2c5: i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4>;
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};
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mux2_i2c6: i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x5>;
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};
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mux2_i2c7: i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x6>;
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};
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mux2_i2c8: i2c@7 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x7>;
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};
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};
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};
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&hdmi {
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ddc-i2c-bus = <&mux2_i2c1>;
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};
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&mux1_i2c1 {
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ads7830@4a {
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compatible = "ti,ads7830";
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reg = <0x4a>;
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};
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};
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&mux2_i2c2 {
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clock-frequency = <100000>;
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stdp2690@72 {
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compatible = "megachips,stdp2690-ge-b850v3-fw";
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reg = <0x72>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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stdp2690_in: endpoint {
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remote-endpoint = <&stdp4028_out>;
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};
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};
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port@1 {
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reg = <1>;
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stdp2690_out: endpoint {
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/* Connector for external display */
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};
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};
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};
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};
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stdp4028@73 {
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compatible = "megachips,stdp4028-ge-b850v3-fw";
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reg = <0x73>;
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interrupt-parent = <&gpio2>;
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interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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stdp4028_in: endpoint {
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remote-endpoint = <&lvds0_out>;
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};
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};
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port@1 {
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reg = <1>;
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stdp4028_out: endpoint {
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remote-endpoint = <&stdp2690_in>;
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};
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};
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};
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};
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};
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&pca9539 {
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P10 {
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gpio-hog;
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gpios = <8 0>;
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output-low;
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line-name = "PCA9539-P10";
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};
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P11 {
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gpio-hog;
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gpios = <9 0>;
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output-low;
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line-name = "PCA9539-P11";
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};
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};
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&pci_root {
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/* PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch */
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bridge@1,0 {
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compatible = "pci10b5,8605";
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reg = <0x00010000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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bridge@2,1 {
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compatible = "pci10b5,8605";
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reg = <0x00020800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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/* Intel Corporation I210 Gigabit Network Connection */
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ethernet@3,0 {
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compatible = "pci8086,1533";
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reg = <0x00030000 0 0 0 0>;
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};
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};
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bridge@2,2 {
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compatible = "pci10b5,8605";
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reg = <0x00021000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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/* Intel Corporation I210 Gigabit Network Connection */
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switch_nic: ethernet@4,0 {
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compatible = "pci8086,1533";
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reg = <0x00040000 0 0 0 0>;
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};
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};
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};
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};
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&switch_ports {
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port@0 {
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reg = <0>;
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label = "eneport1";
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phy-handle = <&switchphy0>;
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};
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port@1 {
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reg = <1>;
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label = "eneport2";
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phy-handle = <&switchphy1>;
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};
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port@2 {
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reg = <2>;
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label = "enix";
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phy-handle = <&switchphy2>;
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};
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port@3 {
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reg = <3>;
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label = "enid";
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phy-handle = <&switchphy3>;
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};
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port@4 {
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reg = <4>;
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label = "cpu";
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ethernet = <&switch_nic>;
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phy-handle = <&switchphy4>;
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};
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};
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#include "imx6q-bx50v3-uboot.dtsi"
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