151 lines
3.5 KiB
Plaintext
151 lines
3.5 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2019 BayLibre, SAS
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* Author: Fabien Parent <fparent@baylibre.com>
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*/
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#include <dt-bindings/clock/mt8516-clk.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "mediatek,mt8516";
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interrupt-parent = <&sysirq>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "mediatek,mt8516-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0>;
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clock-frequency = <1300000000>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x1>;
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clock-frequency = <1300000000>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x2>;
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clock-frequency = <1300000000>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x3>;
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clock-frequency = <1300000000>;
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};
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};
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topckgen: clock-controller@10000000 {
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compatible = "mediatek,mt8516-topckgen";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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};
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topckgen_cg: clock-controller-cg@10000000 {
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compatible = "mediatek,mt8516-topckgen-cg";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: clock-controller@10001000 {
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compatible = "mediatek,mt8516-infracfg";
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reg = <0x10001000 0x1000>;
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#clock-cells = <1>;
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};
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apmixedsys: clock-controller@10018000 {
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compatible = "mediatek,mt8516-apmixedsys";
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reg = <0x10018000 0x710>;
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#clock-cells = <1>;
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};
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gic: interrupt-controller@10310000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0x10310000 0x1000>,
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<0x10320000 0x1000>,
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<0x10340000 0x2000>,
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<0x10360000 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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sysirq: interrupt-controller@10200620 {
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compatible = "mediatek,sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0x10200620 0x20>;
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};
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watchdog: watchdog@10007000 {
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compatible = "mediatek,wdt";
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reg = <0x10007000 0x1000>;
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interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>;
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#reset-cells = <1>;
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status = "disabled";
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};
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pinctrl: pinctrl@10005000 {
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compatible = "mediatek,mt8516-pinctrl";
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reg = <0x10005000 0x1000>;
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gpio: gpio-controller {
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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mmc0: mmc@11120000 {
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compatible = "mediatek,mt8516-mmc";
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reg = <0x11120000 0x1000>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen_cg CLK_TOP_MSDC0>,
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<&topckgen CLK_TOP_AHB_INFRA_SEL>,
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<&topckgen_cg CLK_TOP_MSDC0_INFRA>;
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clock-names = "source", "hclk", "source_cg";
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status = "disabled";
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};
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usb0: usb@11100000 {
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compatible = "mediatek,mt8516-musb",
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"mediatek,mt8518-musb";
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reg = <0x11100000 0x1000>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "mc";
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clocks = <&topckgen CLK_TOP_USB_PHY48M>,
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<&topckgen_cg CLK_TOP_USBIF>,
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<&topckgen_cg CLK_TOP_USB>,
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<&topckgen_cg CLK_TOP_USB_1P>;
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clock-names = "usbpll", "usbmcu", "usb", "icusb";
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status = "disabled";
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};
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uart0: serial@11005000 {
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compatible = "mediatek,hsuart";
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reg = <0x11005000 0x1000>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_UART0_SEL>,
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<&topckgen_cg CLK_TOP_UART0>;
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clock-names = "baud","bus";
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status = "disabled";
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};
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};
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