701 lines
15 KiB
Plaintext
701 lines
15 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
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*
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*/
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#include "armv7-m.dtsi"
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#include <dt-bindings/clock/stm32h7-clks.h>
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#include <dt-bindings/mfd/stm32h7-rcc.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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clk_i2s: i2s_ckin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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};
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soc {
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timer5: timer@40000c00 {
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compatible = "st,stm32-timer";
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reg = <0x40000c00 0x400>;
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interrupts = <50>;
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clocks = <&rcc TIM5_CK>;
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};
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lptimer1: timer@40002400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-lptimer";
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reg = <0x40002400 0x400>;
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clocks = <&rcc LPTIM1_CK>;
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clock-names = "mux";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm-lp";
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#pwm-cells = <3>;
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status = "disabled";
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};
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trigger@0 {
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compatible = "st,stm32-lptimer-trigger";
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reg = <0>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-lptimer-counter";
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status = "disabled";
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};
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};
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spi2: spi@40003800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32h7-spi";
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reg = <0x40003800 0x400>;
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interrupts = <36>;
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resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
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clocks = <&rcc SPI2_CK>;
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status = "disabled";
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};
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spi3: spi@40003c00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32h7-spi";
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reg = <0x40003c00 0x400>;
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interrupts = <51>;
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resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
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clocks = <&rcc SPI3_CK>;
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status = "disabled";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32h7-uart";
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reg = <0x40004400 0x400>;
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interrupts = <38>;
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status = "disabled";
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clocks = <&rcc USART2_CK>;
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};
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usart3: serial@40004800 {
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compatible = "st,stm32h7-uart";
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reg = <0x40004800 0x400>;
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interrupts = <39>;
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status = "disabled";
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clocks = <&rcc USART3_CK>;
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};
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uart4: serial@40004c00 {
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compatible = "st,stm32h7-uart";
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reg = <0x40004c00 0x400>;
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interrupts = <52>;
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status = "disabled";
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clocks = <&rcc UART4_CK>;
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};
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i2c1: i2c@40005400 {
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compatible = "st,stm32f7-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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interrupts = <31>,
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<32>;
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resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
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clocks = <&rcc I2C1_CK>;
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status = "disabled";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32f7-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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interrupts = <33>,
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<34>;
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resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
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clocks = <&rcc I2C2_CK>;
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status = "disabled";
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};
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i2c3: i2c@40005c00 {
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compatible = "st,stm32f7-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005C00 0x400>;
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interrupts = <72>,
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<73>;
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resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
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clocks = <&rcc I2C3_CK>;
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status = "disabled";
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};
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dac: dac@40007400 {
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compatible = "st,stm32h7-dac-core";
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reg = <0x40007400 0x400>;
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clocks = <&rcc DAC12_CK>;
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clock-names = "pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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dac1: dac@1 {
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compatible = "st,stm32-dac";
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#io-channel-cells = <1>;
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reg = <1>;
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status = "disabled";
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};
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dac2: dac@2 {
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compatible = "st,stm32-dac";
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#io-channel-cells = <1>;
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reg = <2>;
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status = "disabled";
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};
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};
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usart1: serial@40011000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40011000 0x400>;
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interrupts = <37>;
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status = "disabled";
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clocks = <&rcc USART1_CK>;
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};
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spi1: spi@40013000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32h7-spi";
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reg = <0x40013000 0x400>;
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interrupts = <35>;
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resets = <&rcc STM32H7_APB2_RESET(SPI1)>;
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clocks = <&rcc SPI1_CK>;
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status = "disabled";
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};
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spi4: spi@40013400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32h7-spi";
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reg = <0x40013400 0x400>;
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interrupts = <84>;
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resets = <&rcc STM32H7_APB2_RESET(SPI4)>;
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clocks = <&rcc SPI4_CK>;
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status = "disabled";
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};
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spi5: spi@40015000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32h7-spi";
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reg = <0x40015000 0x400>;
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interrupts = <85>;
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resets = <&rcc STM32H7_APB2_RESET(SPI5)>;
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clocks = <&rcc SPI5_CK>;
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status = "disabled";
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};
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dma1: dma-controller@40020000 {
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compatible = "st,stm32-dma";
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reg = <0x40020000 0x400>;
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interrupts = <11>,
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<12>,
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<13>,
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<14>,
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<15>,
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<16>,
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<17>,
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<47>;
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clocks = <&rcc DMA1_CK>;
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#dma-cells = <4>;
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st,mem2mem;
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dma-requests = <8>;
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status = "disabled";
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};
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dma2: dma-controller@40020400 {
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compatible = "st,stm32-dma";
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reg = <0x40020400 0x400>;
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interrupts = <56>,
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<57>,
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<58>,
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<59>,
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<60>,
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<68>,
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<69>,
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<70>;
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clocks = <&rcc DMA2_CK>;
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#dma-cells = <4>;
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st,mem2mem;
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dma-requests = <8>;
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status = "disabled";
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};
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dmamux1: dma-router@40020800 {
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compatible = "st,stm32h7-dmamux";
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reg = <0x40020800 0x40>;
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#dma-cells = <3>;
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dma-channels = <16>;
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dma-requests = <128>;
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dma-masters = <&dma1 &dma2>;
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clocks = <&rcc DMA1_CK>;
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};
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adc_12: adc@40022000 {
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compatible = "st,stm32h7-adc-core";
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reg = <0x40022000 0x400>;
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interrupts = <18>;
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clocks = <&rcc ADC12_CK>;
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clock-names = "bus";
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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adc1: adc@0 {
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compatible = "st,stm32h7-adc";
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#io-channel-cells = <1>;
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reg = <0x0>;
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interrupt-parent = <&adc_12>;
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interrupts = <0>;
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status = "disabled";
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};
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adc2: adc@100 {
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compatible = "st,stm32h7-adc";
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#io-channel-cells = <1>;
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reg = <0x100>;
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interrupt-parent = <&adc_12>;
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interrupts = <1>;
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status = "disabled";
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};
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};
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usbotg_hs: usb@40040000 {
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compatible = "st,stm32f7-hsotg";
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reg = <0x40040000 0x40000>;
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interrupts = <77>;
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clocks = <&rcc USB1OTG_CK>;
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clock-names = "otg";
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g-rx-fifo-size = <256>;
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g-np-tx-fifo-size = <32>;
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g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
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status = "disabled";
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};
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usbotg_fs: usb@40080000 {
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compatible = "st,stm32f4x9-fsotg";
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reg = <0x40080000 0x40000>;
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interrupts = <101>;
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clocks = <&rcc USB2OTG_CK>;
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clock-names = "otg";
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status = "disabled";
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};
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ltdc: display-controller@50001000 {
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compatible = "st,stm32-ltdc";
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reg = <0x50001000 0x200>;
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interrupts = <88>, <89>;
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resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
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clocks = <&rcc LTDC_CK>;
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clock-names = "lcd";
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status = "disabled";
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};
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mdma1: dma-controller@52000000 {
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compatible = "st,stm32h7-mdma";
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reg = <0x52000000 0x1000>;
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interrupts = <122>;
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clocks = <&rcc MDMA_CK>;
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#dma-cells = <5>;
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dma-channels = <16>;
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dma-requests = <32>;
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};
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sdmmc1: sdmmc@52007000 {
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x10153180>;
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reg = <0x52007000 0x1000>;
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interrupts = <49>;
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interrupt-names = "cmd_irq";
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clocks = <&rcc SDMMC1_CK>;
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clock-names = "apb_pclk";
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resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <120000000>;
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};
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sdmmc2: sdmmc@48022400 {
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x10153180>;
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reg = <0x48022400 0x400>;
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interrupts = <124>;
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interrupt-names = "cmd_irq";
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clocks = <&rcc SDMMC2_CK>;
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clock-names = "apb_pclk";
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resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <120000000>;
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};
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exti: interrupt-controller@58000000 {
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compatible = "st,stm32h7-exti";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x58000000 0x400>;
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interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
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};
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syscfg: syscon@58000400 {
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compatible = "st,stm32-syscfg", "syscon";
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reg = <0x58000400 0x400>;
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};
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spi6: spi@58001400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32h7-spi";
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reg = <0x58001400 0x400>;
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interrupts = <86>;
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resets = <&rcc STM32H7_APB4_RESET(SPI6)>;
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clocks = <&rcc SPI6_CK>;
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status = "disabled";
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};
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i2c4: i2c@58001c00 {
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compatible = "st,stm32f7-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x58001C00 0x400>;
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interrupts = <95>,
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<96>;
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resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
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clocks = <&rcc I2C4_CK>;
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status = "disabled";
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};
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lptimer2: timer@58002400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-lptimer";
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reg = <0x58002400 0x400>;
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clocks = <&rcc LPTIM2_CK>;
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clock-names = "mux";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm-lp";
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#pwm-cells = <3>;
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status = "disabled";
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};
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trigger@1 {
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compatible = "st,stm32-lptimer-trigger";
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reg = <1>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-lptimer-counter";
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status = "disabled";
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};
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};
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lptimer3: timer@58002800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-lptimer";
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reg = <0x58002800 0x400>;
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clocks = <&rcc LPTIM3_CK>;
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clock-names = "mux";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm-lp";
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#pwm-cells = <3>;
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status = "disabled";
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};
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trigger@2 {
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compatible = "st,stm32-lptimer-trigger";
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reg = <2>;
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status = "disabled";
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};
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};
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lptimer4: timer@58002c00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-lptimer";
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reg = <0x58002c00 0x400>;
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clocks = <&rcc LPTIM4_CK>;
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clock-names = "mux";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm-lp";
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#pwm-cells = <3>;
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status = "disabled";
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};
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};
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lptimer5: timer@58003000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-lptimer";
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reg = <0x58003000 0x400>;
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clocks = <&rcc LPTIM5_CK>;
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clock-names = "mux";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm-lp";
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#pwm-cells = <3>;
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status = "disabled";
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};
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};
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vrefbuf: regulator@58003c00 {
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compatible = "st,stm32-vrefbuf";
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reg = <0x58003C00 0x8>;
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clocks = <&rcc VREF_CK>;
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <2500000>;
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status = "disabled";
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};
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rtc: rtc@58004000 {
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compatible = "st,stm32h7-rtc";
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reg = <0x58004000 0x400>;
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clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
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clock-names = "pclk", "rtc_ck";
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assigned-clocks = <&rcc RTC_CK>;
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assigned-clock-parents = <&rcc LSE_CK>;
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interrupt-parent = <&exti>;
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interrupts = <17 IRQ_TYPE_EDGE_RISING>;
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st,syscfg = <&pwrcfg 0x00 0x100>;
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status = "disabled";
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};
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rcc: reset-clock-controller@58024400 {
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compatible = "st,stm32h743-rcc", "st,stm32-rcc";
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reg = <0x58024400 0x400>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
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st,syscfg = <&pwrcfg>;
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};
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pwrcfg: power-config@58024800 {
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compatible = "st,stm32-power-config", "syscon";
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reg = <0x58024800 0x400>;
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};
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adc_3: adc@58026000 {
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compatible = "st,stm32h7-adc-core";
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reg = <0x58026000 0x400>;
|
|
interrupts = <127>;
|
|
clocks = <&rcc ADC3_CK>;
|
|
clock-names = "bus";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
adc3: adc@0 {
|
|
compatible = "st,stm32h7-adc";
|
|
#io-channel-cells = <1>;
|
|
reg = <0x0>;
|
|
interrupt-parent = <&adc_3>;
|
|
interrupts = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
mac: ethernet@40028000 {
|
|
compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
|
|
reg = <0x40028000 0x8000>;
|
|
reg-names = "stmmaceth";
|
|
interrupts = <61>;
|
|
interrupt-names = "macirq";
|
|
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
|
|
clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>;
|
|
st,syscon = <&syscfg 0x4>;
|
|
snps,pbl = <8>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pinctrl: pin-controller@58020000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "st,stm32h743-pinctrl";
|
|
ranges = <0 0x58020000 0x3000>;
|
|
interrupt-parent = <&exti>;
|
|
st,syscfg = <&syscfg 0x8>;
|
|
pins-are-numbered;
|
|
|
|
gpioa: gpio@58020000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x0 0x400>;
|
|
clocks = <&rcc GPIOA_CK>;
|
|
st,bank-name = "GPIOA";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
ngpios = <16>;
|
|
gpio-ranges = <&pinctrl 0 0 16>;
|
|
};
|
|
|
|
gpiob: gpio@58020400 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x400 0x400>;
|
|
clocks = <&rcc GPIOB_CK>;
|
|
st,bank-name = "GPIOB";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
ngpios = <16>;
|
|
gpio-ranges = <&pinctrl 0 16 16>;
|
|
};
|
|
|
|
gpioc: gpio@58020800 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x800 0x400>;
|
|
clocks = <&rcc GPIOC_CK>;
|
|
st,bank-name = "GPIOC";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
ngpios = <16>;
|
|
gpio-ranges = <&pinctrl 0 32 16>;
|
|
};
|
|
|
|
gpiod: gpio@58020c00 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0xc00 0x400>;
|
|
clocks = <&rcc GPIOD_CK>;
|
|
st,bank-name = "GPIOD";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
ngpios = <16>;
|
|
gpio-ranges = <&pinctrl 0 48 16>;
|
|
};
|
|
|
|
gpioe: gpio@58021000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x1000 0x400>;
|
|
clocks = <&rcc GPIOE_CK>;
|
|
st,bank-name = "GPIOE";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
ngpios = <16>;
|
|
gpio-ranges = <&pinctrl 0 64 16>;
|
|
};
|
|
|
|
gpiof: gpio@58021400 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x1400 0x400>;
|
|
clocks = <&rcc GPIOF_CK>;
|
|
st,bank-name = "GPIOF";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
ngpios = <16>;
|
|
gpio-ranges = <&pinctrl 0 80 16>;
|
|
};
|
|
|
|
gpiog: gpio@58021800 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x1800 0x400>;
|
|
clocks = <&rcc GPIOG_CK>;
|
|
st,bank-name = "GPIOG";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
ngpios = <16>;
|
|
gpio-ranges = <&pinctrl 0 96 16>;
|
|
};
|
|
|
|
gpioh: gpio@58021c00 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x1c00 0x400>;
|
|
clocks = <&rcc GPIOH_CK>;
|
|
st,bank-name = "GPIOH";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
ngpios = <16>;
|
|
gpio-ranges = <&pinctrl 0 112 16>;
|
|
};
|
|
|
|
gpioi: gpio@58022000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x2000 0x400>;
|
|
clocks = <&rcc GPIOI_CK>;
|
|
st,bank-name = "GPIOI";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
ngpios = <16>;
|
|
gpio-ranges = <&pinctrl 0 128 16>;
|
|
};
|
|
|
|
gpioj: gpio@58022400 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x2400 0x400>;
|
|
clocks = <&rcc GPIOJ_CK>;
|
|
st,bank-name = "GPIOJ";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
ngpios = <16>;
|
|
gpio-ranges = <&pinctrl 0 144 16>;
|
|
};
|
|
|
|
gpiok: gpio@58022800 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x2800 0x400>;
|
|
clocks = <&rcc GPIOK_CK>;
|
|
st,bank-name = "GPIOK";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
ngpios = <8>;
|
|
gpio-ranges = <&pinctrl 0 160 8>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&systick {
|
|
clock-frequency = <250000000>;
|
|
status = "okay";
|
|
};
|