59 lines
1.8 KiB
C
59 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* K3: AM64 SoC definitions, structures etc.
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*
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* (C) Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef __ASM_ARCH_AM64_HARDWARE_H
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#define __ASM_ARCH_AM64_HARDWARE_H
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#define CTRL_MMR0_BASE 0x43000000
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#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
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#define PADCFG_MMR1_BASE 0xf0000
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK 0x00000078
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK 0x00000380
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#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7
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#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK 0x00001c00
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#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
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#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK 0x00002000
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#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13
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/* After the cfg mask and shifts have been applied */
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#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2
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#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x04
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#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1
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#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02
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#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01
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/*
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* The CTRL_MMR and PADCFG_MMR memory space is divided into several
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* equally-spaced partitions, so defining the partition size allows us to
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* determine register addresses common to those partitions.
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*/
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#define CTRL_MMR0_PARTITION_SIZE 0x4000
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/*
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* CTRL_MMR and PADCFG_MMR lock/kick-mechanism shared register definitions.
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*/
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#define CTRLMMR_LOCK_KICK0 0x01008
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#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
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#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
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#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
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#define CTRLMMR_LOCK_KICK1 0x0100c
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#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
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#define ROM_ENTENDED_BOOT_DATA_INFO 0x701beb00
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/* Use Last 2K as Scratch pad */
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#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x7019f800
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#endif /* __ASM_ARCH_DRA8_HARDWARE_H */
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