274 lines
8.1 KiB
C
274 lines
8.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+
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*
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* Copyright (C) 2016 Nexell Co., Ltd.
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*
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* Author: junghyun, kim <jhkim@nexell.co.kr>
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*/
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#ifndef _NX__DISPLAY_H_
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#define _NX__DISPLAY_H_
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#define DP_PLANS_NUM 3
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/* the display output format. */
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#define DPC_FORMAT_RGB555 0 /* RGB555 Format */
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#define DPC_FORMAT_RGB565 1 /* RGB565 Format */
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#define DPC_FORMAT_RGB666 2 /* RGB666 Format */
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#define DPC_FORMAT_RGB888 3 /* RGB888 Format */
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#define DPC_FORMAT_MRGB555A 4 /* MRGB555A Format */
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#define DPC_FORMAT_MRGB555B 5 /* MRGB555B Format */
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#define DPC_FORMAT_MRGB565 6 /* MRGB565 Format */
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#define DPC_FORMAT_MRGB666 7 /* MRGB666 Format */
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#define DPC_FORMAT_MRGB888A 8 /* MRGB888A Format */
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#define DPC_FORMAT_MRGB888B 9 /* MRGB888B Format */
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#define DPC_FORMAT_CCIR656 10 /* ITU-R BT.656 / 601(8-bit) */
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#define DPC_FORMAT_CCIR601A 12 /* ITU-R BT.601A */
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#define DPC_FORMAT_CCIR601B 13 /* ITU-R BT.601B */
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#define DPC_FORMAT_4096COLOR 1 /* 4096 Color Format */
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#define DPC_FORMAT_16GRAY 3 /* 16 Level Gray Format */
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/* layer pixel format. */
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#define MLC_RGBFMT_R5G6B5 0x44320000 /* {R5,G6,B5 }. */
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#define MLC_RGBFMT_B5G6R5 0xC4320000 /* {B5,G6,R5 }. */
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#define MLC_RGBFMT_X1R5G5B5 0x43420000 /* {X1,R5,G5,B5}. */
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#define MLC_RGBFMT_X1B5G5R5 0xC3420000 /* {X1,B5,G5,R5}. */
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#define MLC_RGBFMT_X4R4G4B4 0x42110000 /* {X4,R4,G4,B4}. */
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#define MLC_RGBFMT_X4B4G4R4 0xC2110000 /* {X4,B4,G4,R4}. */
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#define MLC_RGBFMT_X8R3G3B2 0x41200000 /* {X8,R3,G3,B2}. */
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#define MLC_RGBFMT_X8B3G3R2 0xC1200000 /* {X8,B3,G3,R2}. */
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#define MLC_RGBFMT_A1R5G5B5 0x33420000 /* {A1,R5,G5,B5}. */
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#define MLC_RGBFMT_A1B5G5R5 0xB3420000 /* {A1,B5,G5,R5}. */
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#define MLC_RGBFMT_A4R4G4B4 0x22110000 /* {A4,R4,G4,B4}. */
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#define MLC_RGBFMT_A4B4G4R4 0xA2110000 /* {A4,B4,G4,R4}. */
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#define MLC_RGBFMT_A8R3G3B2 0x11200000 /* {A8,R3,G3,B2}. */
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#define MLC_RGBFMT_A8B3G3R2 0x91200000 /* {A8,B3,G3,R2}. */
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#define MLC_RGBFMT_R8G8B8 0x46530000 /* {R8,G8,B8 }. */
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#define MLC_RGBFMT_B8G8R8 0xC6530000 /* {B8,G8,R8 }. */
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#define MLC_RGBFMT_X8R8G8B8 0x46530000 /* {X8,R8,G8,B8}. */
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#define MLC_RGBFMT_X8B8G8R8 0xC6530000 /* {X8,B8,G8,R8}. */
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#define MLC_RGBFMT_A8R8G8B8 0x06530000 /* {A8,R8,G8,B8}. */
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#define MLC_RGBFMT_A8B8G8R8 0x86530000 /* {A8,B8,G8,R8}. */
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/* the data output order in case of ITU-R BT.656 / 601. */
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#define DPC_YCORDER_CBYCRY 0
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#define DPC_YCORDER_CRYCBY 1
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#define DPC_YCORDER_YCBYCR 2
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#define DPC_YCORDER_YCRYCB 3
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/* the PAD output clock. */
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#define DPC_PADCLKSEL_VCLK 0 /* VCLK */
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#define DPC_PADCLKSEL_VCLK2 1 /* VCLK2 */
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/* display sync info for DPC */
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struct dp_sync_info {
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int interlace;
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int h_active_len;
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int h_sync_width;
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int h_back_porch;
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int h_front_porch;
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int h_sync_invert; /* default active low */
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int v_active_len;
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int v_sync_width;
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int v_back_porch;
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int v_front_porch;
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int v_sync_invert; /* default active low */
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int pixel_clock_hz; /* HZ */
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};
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/* syncgen control (DPC) */
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#define DP_SYNC_DELAY_RGB_PVD (1 << 0)
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#define DP_SYNC_DELAY_HSYNC_CP1 (1 << 1)
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#define DP_SYNC_DELAY_VSYNC_FRAM (1 << 2)
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#define DP_SYNC_DELAY_DE_CP (1 << 3)
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struct dp_ctrl_info {
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/* clock gen */
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int clk_src_lv0;
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int clk_div_lv0;
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int clk_src_lv1;
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int clk_div_lv1;
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/* scan format */
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int interlace;
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/* syncgen format */
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unsigned int out_format;
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int invert_field; /* 0:normal(Low odd), 1:invert (low even) */
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int swap_RB;
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unsigned int yc_order; /* for CCIR output */
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/* extern sync delay */
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int delay_mask; /* if 0, set defalut delays */
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int d_rgb_pvd; /* delay for RGB/PVD, 0~16, default 0 */
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int d_hsync_cp1; /* delay for HSYNC/CP1, 0~63, default 12 */
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int d_vsync_fram; /* delay for VSYNC/FRAM, 0~63, default 12 */
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int d_de_cp2; /* delay for DE/CP2, 0~63, default 12 */
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/* sync offset */
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int vs_start_offset; /* start vsync offset, defatult 0 */
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int vs_end_offset; /* end vsync offset, default 0 */
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int ev_start_offset; /* start even vsync offset, default 0 */
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int ev_end_offset; /* end even vsync offset , default 0 */
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/* pad clock seletor */
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int vck_select; /* 0=vclk0, 1=vclk2 */
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int clk_inv_lv0; /* OUTCLKINVn */
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int clk_delay_lv0; /* OUTCLKDELAYn */
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int clk_inv_lv1; /* OUTCLKINVn */
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int clk_delay_lv1; /* OUTCLKDELAYn */
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int clk_sel_div1; /* 0=clk1_inv, 1=clk1_div_2_ns */
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};
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/* multi layer control (MLC) */
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struct dp_plane_top {
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int screen_width;
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int screen_height;
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int video_prior; /* 0: video>RGBn, 1: RGB0>video>RGB1,
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* 2: RGB0 > RGB1 > video .. */
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int interlace;
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int plane_num;
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unsigned int back_color;
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};
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struct dp_plane_info {
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int layer;
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unsigned int fb_base;
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int left;
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int top;
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int width;
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int height;
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int pixel_byte;
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unsigned int format;
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int alpha_on;
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int alpha_depth;
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int tp_on; /* transparency color enable */
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unsigned int tp_color;
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unsigned int mem_lock_size; /* memory burst access (4,8,16) */
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int video_layer;
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int enable;
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};
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/*
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* LCD device dependency struct
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* RGB, LVDS, MiPi, HDMI
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*/
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enum {
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DP_DEVICE_RESCONV = 0,
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DP_DEVICE_RGBLCD = 1,
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DP_DEVICE_HDMI = 2,
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DP_DEVICE_MIPI = 3,
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DP_DEVICE_LVDS = 4,
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DP_DEVICE_CVBS = 5,
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DP_DEVICE_DP0 = 6,
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DP_DEVICE_DP1 = 7,
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DP_DEVICE_END,
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};
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enum {
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DP_CLOCK_RESCONV = 0,
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DP_CLOCK_LCDIF = 1,
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DP_CLOCK_MIPI = 2,
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DP_CLOCK_LVDS = 3,
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DP_CLOCK_HDMI = 4,
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DP_CLOCK_END,
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};
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enum dp_lvds_format {
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DP_LVDS_FORMAT_VESA = 0,
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DP_LVDS_FORMAT_JEIDA = 1,
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DP_LVDS_FORMAT_LOC = 2,
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};
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#define DEF_VOLTAGE_LEVEL (0x20)
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struct dp_lvds_dev {
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enum dp_lvds_format lvds_format; /* 0:VESA, 1:JEIDA, 2: Location */
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int pol_inv_hs; /* hsync polarity invert for VESA, JEIDA */
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int pol_inv_vs; /* bsync polarity invert for VESA, JEIDA */
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int pol_inv_de; /* de polarity invert for VESA, JEIDA */
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int pol_inv_ck; /* input clock(pixel clock) polarity invert */
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int voltage_level;
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/* Location setting */
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unsigned int loc_map[9]; /* Location Setting */
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unsigned int loc_mask[2]; /* Location Setting, 0 ~ 34 */
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unsigned int loc_pol[2]; /* Location Setting, 0 ~ 34 */
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};
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#include "mipi_display.h"
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struct dp_mipi_dev {
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int lp_bitrate; /* to lcd setup, low power bitrate (150, 100, 80 Mhz) */
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int hs_bitrate; /* to lcd data, high speed bitrate (1000, ... Mhz) */
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int lpm_trans;
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int command_mode;
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unsigned int hs_pllpms;
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unsigned int hs_bandctl;
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unsigned int lp_pllpms;
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unsigned int lp_bandctl;
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struct mipi_dsi_device dsi;
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};
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struct dp_rgb_dev {
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int lcd_mpu_type;
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};
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struct dp_hdmi_dev {
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int preset;
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};
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/* platform data for the driver model */
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struct nx_display_plat {
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int module;
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struct dp_sync_info sync;
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struct dp_ctrl_info ctrl;
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struct dp_plane_top top;
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struct dp_plane_info plane[DP_PLANS_NUM];
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int dev_type;
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void *device;
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};
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/* Lcd api */
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void nx_lvds_display(int module,
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struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
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struct dp_plane_top *top,
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struct dp_plane_info *planes,
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struct dp_lvds_dev *dev);
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void nx_rgb_display(int module,
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struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
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struct dp_plane_top *top, struct dp_plane_info *planes,
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struct dp_rgb_dev *dev);
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void nx_hdmi_display(int module,
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struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
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struct dp_plane_top *top,
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struct dp_plane_info *planes,
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struct dp_hdmi_dev *dev);
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void nx_mipi_display(int module,
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struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
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struct dp_plane_top *top,
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struct dp_plane_info *planes,
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struct dp_mipi_dev *dev);
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int nx_mipi_dsi_lcd_bind(struct mipi_dsi_device *dsi);
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/* disaply api */
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void dp_control_init(int module);
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int dp_control_setup(int module, struct dp_sync_info *sync,
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struct dp_ctrl_info *ctrl);
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void dp_control_enable(int module, int on);
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void dp_plane_init(int module);
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int dp_plane_screen_setup(int module, struct dp_plane_top *top);
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void dp_plane_screen_enable(int module, int on);
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int dp_plane_layer_setup(int module, struct dp_plane_info *plane);
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void dp_plane_layer_enable(int module, struct dp_plane_info *plane, int on);
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int dp_plane_set_enable(int module, int layer, int on);
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int dp_plane_set_address(int module, int layer, unsigned int address);
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int dp_plane_wait_vsync(int module, int layer, int fps);
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#if defined CONFIG_SPL_BUILD || \
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(!defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL))
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int nx_display_probe(struct nx_display_plat *plat);
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#endif
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#endif
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