169 lines
4.0 KiB
C
169 lines
4.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Author :
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* Vaibhav Hiremath <hvaibhav@ti.com>
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*
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* Based on mem.c and sdrc.c
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*
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* Copyright (C) 2010
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* Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/emif4.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern omap3_sysinfo sysinfo;
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static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE;
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/*
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* is_mem_sdr -
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* - Return 1 if mem type in use is SDR
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*/
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u32 is_mem_sdr(void)
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{
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return 0;
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}
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/*
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* get_sdr_cs_size -
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* - Get size of chip select 0/1
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*/
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u32 get_sdr_cs_size(u32 cs)
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{
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u32 size = 0;
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/* TODO: Calculate the size based on EMIF4 configuration */
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if (cs == CS0)
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size = CONFIG_SYS_CS0_SIZE;
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return size;
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}
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/*
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* get_sdr_cs_offset -
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* - Get offset of cs from cs0 start
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*/
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u32 get_sdr_cs_offset(u32 cs)
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{
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u32 offset = 0;
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return offset;
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}
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/*
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* do_emif4_init -
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* - Init the emif4 module for DDR access
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* - Early init routines, called from flash or SRAM.
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*/
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static void do_emif4_init(void)
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{
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unsigned int regval;
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/* Set the DDR PHY parameters in PHY ctrl registers */
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regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
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EMIF4_DDR1_EXT_STRB_DIS);
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writel(regval, &emif4_base->ddr_phyctrl1);
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writel(regval, &emif4_base->ddr_phyctrl1_shdw);
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writel(0, &emif4_base->ddr_phyctrl2);
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/* Reset the DDR PHY and wait till completed */
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regval = readl(&emif4_base->sdram_iodft_tlgc);
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regval |= (1<<10);
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writel(regval, &emif4_base->sdram_iodft_tlgc);
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/*Wait till that bit clears*/
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while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) != 0x0);
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/*Re-verify the DDR PHY status*/
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while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0);
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regval |= (1<<0);
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writel(regval, &emif4_base->sdram_iodft_tlgc);
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/* Set SDR timing registers */
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regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
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EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
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EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
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EMIF4_TIM1_T_RP);
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writel(regval, &emif4_base->sdram_time1);
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writel(regval, &emif4_base->sdram_time1_shdw);
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regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
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EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
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EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
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writel(regval, &emif4_base->sdram_time2);
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writel(regval, &emif4_base->sdram_time2_shdw);
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regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
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writel(regval, &emif4_base->sdram_time3);
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writel(regval, &emif4_base->sdram_time3_shdw);
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/* Set the PWR control register */
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regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
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EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
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writel(regval, &emif4_base->sdram_pwr_mgmt);
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writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);
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/* Set the DDR refresh rate control register */
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regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
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writel(regval, &emif4_base->sdram_refresh_ctrl);
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writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);
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/* set the SDRAM configuration register */
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regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
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EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
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EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
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EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
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EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
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EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
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writel(regval, &emif4_base->sdram_config);
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}
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/*
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* dram_init -
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* - Sets uboots idea of sdram size
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*/
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int dram_init(void)
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{
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unsigned int size0 = 0, size1 = 0;
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size0 = get_sdr_cs_size(CS0);
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/*
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* If a second bank of DDR is attached to CS1 this is
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* where it can be started. Early init code will init
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* memory on CS0.
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*/
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if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
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size1 = get_sdr_cs_size(CS1);
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gd->ram_size = size0 + size1;
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return 0;
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}
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int dram_init_banksize(void)
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{
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unsigned int size0 = 0, size1 = 0;
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size0 = get_sdr_cs_size(CS0);
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size1 = get_sdr_cs_size(CS1);
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = size0;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
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gd->bd->bi_dram[1].size = size1;
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return 0;
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}
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/*
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* mem_init() -
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* - Initialize memory subsystem
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*/
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void mem_init(void)
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{
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do_emif4_init();
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}
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