299 lines
8.9 KiB
C
299 lines
8.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
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*
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* Based on original Kirkwood support which is
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <init.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <u-boot/md5.h>
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#include <asm/arch/cpu.h>
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#define BUFLEN 16
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void reset_cpu(void)
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{
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struct orion5x_cpu_registers *cpureg =
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(struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
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writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
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&cpureg->rstoutn_mask);
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writel(readl(&cpureg->sys_soft_rst) | 1,
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&cpureg->sys_soft_rst);
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while (1)
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;
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}
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/*
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* Compute Window Size field value from size expressed in bytes
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* Used with the Base register to set the address window size and location.
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* Must be programmed from LSB to MSB as sequence of ones followed by
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* sequence of zeros. The number of ones specifies the size of the window in
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* 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB).
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* NOTES:
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* 1) A sizeval equal to 0x0 specifies 4 GiB.
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* 2) A return value of 0x0 specifies 64 KiB.
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*/
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unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
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{
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/*
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* Calculate the number of 64 KiB blocks needed minus one (rounding up).
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* For sizeval > 0 this is equivalent to:
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* sizeval = (u32) ceil((double) sizeval / 65536.0) - 1
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*/
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sizeval = (sizeval - 1) >> 16;
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/*
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* Propagate 'one' bits to the right by 'oring' them.
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* We need only treat bits 15-0.
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*/
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sizeval |= sizeval >> 1; /* 'Or' bit 15 onto bit 14 */
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sizeval |= sizeval >> 2; /* 'Or' bits 15-14 onto bits 13-12 */
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sizeval |= sizeval >> 4; /* 'Or' bits 15-12 onto bits 11-8 */
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sizeval |= sizeval >> 8; /* 'Or' bits 15-8 onto bits 7-0*/
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return sizeval;
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}
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/*
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* orion5x_config_adr_windows - Configure address Windows
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*
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* There are 8 address windows supported by Orion5x Soc to addess different
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* devices. Each window can be configured for size, BAR and remap addr
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* Below configuration is standard for most of the cases
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*
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* If remap function not used, remap_lo must be set as base
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*
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* NOTES:
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*
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* 1) in order to avoid windows with inconsistent control and base values
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* (which could prevent access to BOOTCS and hence execution from FLASH)
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* always disable window before writing the base value then reenable it
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* by writing the control value.
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*
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* 2) in order to avoid losing access to BOOTCS when disabling window 7,
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* first configure window 6 for BOOTCS, then configure window 7 for BOOTCS,
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* then configure windows 6 for its own target.
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*
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* Reference Documentation:
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* Mbus-L to Mbus Bridge Registers Configuration.
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* (Sec 25.1 and 25.3 of Datasheet)
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*/
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int orion5x_config_adr_windows(void)
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{
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struct orion5x_win_registers *winregs =
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(struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
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/* Disable window 0, configure it for its intended target, enable it. */
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writel(0, &winregs[0].ctrl);
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writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
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writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
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writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
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ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
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ORION5X_WIN_ENABLE), &winregs[0].ctrl);
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/* Disable window 1, configure it for its intended target, enable it. */
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writel(0, &winregs[1].ctrl);
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writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
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writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
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writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
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ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
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ORION5X_WIN_ENABLE), &winregs[1].ctrl);
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/* Disable window 2, configure it for its intended target, enable it. */
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writel(0, &winregs[2].ctrl);
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writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
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ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
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ORION5X_WIN_ENABLE), &winregs[2].ctrl);
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/* Disable window 3, configure it for its intended target, enable it. */
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writel(0, &winregs[3].ctrl);
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writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
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ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
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ORION5X_WIN_ENABLE), &winregs[3].ctrl);
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/* Disable window 4, configure it for its intended target, enable it. */
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writel(0, &winregs[4].ctrl);
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writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
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ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
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ORION5X_WIN_ENABLE), &winregs[4].ctrl);
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/* Disable window 5, configure it for its intended target, enable it. */
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writel(0, &winregs[5].ctrl);
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writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
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ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
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ORION5X_WIN_ENABLE), &winregs[5].ctrl);
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/* Disable window 6, configure it for FLASH, enable it. */
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writel(0, &winregs[6].ctrl);
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writel(ORION5X_ADR_BOOTROM, &winregs[6].base);
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
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ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
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ORION5X_WIN_ENABLE), &winregs[6].ctrl);
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/* Disable window 7, configure it for FLASH, enable it. */
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writel(0, &winregs[7].ctrl);
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writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
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ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
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ORION5X_WIN_ENABLE), &winregs[7].ctrl);
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/* Disable window 6, configure it for its intended target, enable it. */
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writel(0, &winregs[6].ctrl);
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writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
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writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
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ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
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ORION5X_WIN_ENABLE), &winregs[6].ctrl);
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return 0;
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}
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/*
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* Orion5x identification is done through PCIE space.
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*/
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u32 orion5x_device_id(void)
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{
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return readl(PCIE_DEV_ID_OFF) >> 16;
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}
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u32 orion5x_device_rev(void)
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{
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return readl(PCIE_DEV_REV_OFF) & 0xff;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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/* Display device and revision IDs.
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* This function must cover all known device/revision
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* combinations, not only the one for which u-boot is
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* compiled; this way, one can identify actual HW in
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* case of a mismatch.
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*/
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int print_cpuinfo(void)
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{
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char dev_str[7]; /* room enough for 0x0000 plus null byte */
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char rev_str[5]; /* room enough for 0x00 plus null byte */
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char *dev_name = NULL;
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char *rev_name = NULL;
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u32 dev = orion5x_device_id();
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u32 rev = orion5x_device_rev();
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if (dev == MV88F5181_DEV_ID) {
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dev_name = "MV88F5181";
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if (rev == MV88F5181_REV_B1)
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rev_name = "B1";
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else if (rev == MV88F5181L_REV_A1) {
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dev_name = "MV88F5181L";
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rev_name = "A1";
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} else if (rev == MV88F5181L_REV_A0) {
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dev_name = "MV88F5181L";
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rev_name = "A0";
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}
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} else if (dev == MV88F5182_DEV_ID) {
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dev_name = "MV88F5182";
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if (rev == MV88F5182_REV_A2)
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rev_name = "A2";
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} else if (dev == MV88F5281_DEV_ID) {
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dev_name = "MV88F5281";
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if (rev == MV88F5281_REV_D2)
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rev_name = "D2";
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else if (rev == MV88F5281_REV_D1)
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rev_name = "D1";
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else if (rev == MV88F5281_REV_D0)
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rev_name = "D0";
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} else if (dev == MV88F6183_DEV_ID) {
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dev_name = "MV88F6183";
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if (rev == MV88F6183_REV_B0)
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rev_name = "B0";
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}
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if (dev_name == NULL) {
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sprintf(dev_str, "0x%04x", dev);
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dev_name = dev_str;
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}
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if (rev_name == NULL) {
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sprintf(rev_str, "0x%02x", rev);
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rev_name = rev_str;
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}
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printf("SoC: Orion5x %s-%s\n", dev_name, rev_name);
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return 0;
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}
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#endif /* CONFIG_DISPLAY_CPUINFO */
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#ifdef CONFIG_ARCH_CPU_INIT
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int arch_cpu_init(void)
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{
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/* Enable and invalidate L2 cache in write through mode */
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invalidate_l2_cache();
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#ifdef CONFIG_SPL_BUILD
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orion5x_config_adr_windows();
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#endif
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return 0;
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}
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#endif /* CONFIG_ARCH_CPU_INIT */
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/*
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* SOC specific misc init
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*/
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#if defined(CONFIG_ARCH_MISC_INIT)
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int arch_misc_init(void)
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{
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u32 temp;
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/*CPU streaming & write allocate */
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temp = readfr_extra_feature_reg();
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temp &= ~(1 << 28); /* disable wr alloc */
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writefr_extra_feature_reg(temp);
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temp = readfr_extra_feature_reg();
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temp &= ~(1 << 29); /* streaming disabled */
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writefr_extra_feature_reg(temp);
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/* L2Cache settings */
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temp = readfr_extra_feature_reg();
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/* Disable L2C pre fetch - Set bit 24 */
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temp |= (1 << 24);
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/* enable L2C - Set bit 22 */
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temp |= (1 << 22);
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writefr_extra_feature_reg(temp);
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icache_enable();
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/* Change reset vector to address 0x0 */
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temp = get_cr();
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set_cr(temp & ~CR_V);
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/* Set CPIOs and MPPs - values provided by board
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include file */
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writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00);
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writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04);
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writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
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writel(ORION5X_GPIO_OUT_VALUE, ORION5X_GPIO_BASE+0x00);
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writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
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writel(ORION5X_GPIO_IN_POLARITY, ORION5X_GPIO_BASE+0x0c);
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/* initialize timer */
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timer_init_r();
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return 0;
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}
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#endif /* CONFIG_ARCH_MISC_INIT */
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#ifdef CONFIG_MVGBE
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int cpu_eth_init(struct bd_info *bis)
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{
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mvgbe_initialize(bis);
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return 0;
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}
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#endif
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