138 lines
2.9 KiB
C
138 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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*
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* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <asm/global_data.h>
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#include <asm/processor.h>
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#include <asm/immap.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Low Power Divider specifications
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*/
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#define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
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#define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
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#define CLOCK_PLL_FVCO_MAX 540000000
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#define CLOCK_PLL_FVCO_MIN 300000000
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#define CLOCK_PLL_FSYS_MAX 266666666
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#define CLOCK_PLL_FSYS_MIN 100000000
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#define MHZ 1000000
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void clock_enter_limp(int lpdiv)
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{
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ccm_t *ccm = (ccm_t *)MMAP_CCM;
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int i, j;
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/* Check bounds of divider */
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if (lpdiv < CLOCK_LPD_MIN)
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lpdiv = CLOCK_LPD_MIN;
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if (lpdiv > CLOCK_LPD_MAX)
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lpdiv = CLOCK_LPD_MAX;
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/* Round divider down to nearest power of two */
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for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
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/* Enable Limp Mode */
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setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
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}
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/*
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* brief Exit Limp mode
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* warning The PLL should be set and locked prior to exiting Limp mode
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*/
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void clock_exit_limp(void)
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{
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ccm_t *ccm = (ccm_t *)MMAP_CCM;
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pll_t *pll = (pll_t *)MMAP_PLL;
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/* Exit Limp mode */
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clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
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/* Wait for the PLL to lock */
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while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
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;
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}
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#ifdef CONFIG_MCF5441x
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void setup_5441x_clocks(void)
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{
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ccm_t *ccm = (ccm_t *)MMAP_CCM;
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pll_t *pll = (pll_t *)MMAP_PLL;
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int temp, vco = 0, bootmod_ccr, pdr;
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bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14;
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switch (bootmod_ccr) {
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case 0:
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out_be32(&pll->pcr, 0x00000013);
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out_be32(&pll->pdr, 0x00e70c61);
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clock_exit_limp();
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break;
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case 2:
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break;
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case 3:
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break;
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}
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/*Change frequency for Modelo SER1 USB host*/
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#ifdef CONFIG_LOW_MCFCLK
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temp = in_be32(&pll->pcr);
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temp &= ~0x3f;
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temp |= 5;
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out_be32(&pll->pcr, temp);
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temp = in_be32(&pll->pdr);
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temp &= ~0x001f0000;
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temp |= 0x00040000;
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out_be32(&pll->pdr, temp);
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__asm__("tpf");
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#endif
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setbits_be16(&ccm->misccr2, 0x02);
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vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) *
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CONFIG_SYS_INPUT_CLKSRC;
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gd->arch.vco_clk = vco;
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gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
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pdr = in_be32(&pll->pdr);
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temp = (pdr & PLL_DR_OUTDIV1_BITS) + 1;
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gd->cpu_clk = vco / temp; /* cpu clock */
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gd->arch.flb_clk = vco / temp; /* FlexBus clock */
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gd->arch.flb_clk >>= 1;
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if (in_be16(&ccm->misccr2) & 2) /* fsys/4 */
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gd->arch.flb_clk >>= 1;
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temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
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gd->bus_clk = vco / temp; /* bus clock */
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temp = ((pdr & PLL_DR_OUTDIV3_BITS) >> 10) + 1;
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gd->arch.sdhc_clk = vco / temp;
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}
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#endif
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/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
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int get_clocks(void)
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{
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#ifdef CONFIG_MCF5441x
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setup_5441x_clocks();
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#endif
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#ifdef CONFIG_SYS_FSL_I2C
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gd->arch.i2c1_clk = gd->bus_clk;
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#endif
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return (0);
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}
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