57 lines
896 B
C
57 lines
896 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#ifndef _MTMIPS_DDR_H_
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#define _MTMIPS_DDR_H_
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#include <linux/io.h>
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#include <linux/types.h>
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enum mc_dram_size {
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DRAM_8MB,
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DRAM_16MB,
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DRAM_32MB,
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DRAM_64MB,
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DRAM_128MB,
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DRAM_256MB,
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__DRAM_SZ_MAX
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};
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struct mc_ddr_cfg {
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u32 cfg0;
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u32 cfg1;
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u32 cfg2;
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u32 cfg3;
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u32 cfg4;
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};
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typedef void (*mc_reset_t)(int assert);
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struct mc_ddr_init_param {
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void __iomem *memc;
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u32 sdr_cfg0;
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u32 sdr_cfg1;
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u32 dq_dly;
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u32 dqs_dly;
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const struct mc_ddr_cfg *cfgs;
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mc_reset_t mc_reset;
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u32 memsize;
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u32 bus_width;
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};
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void sdr_init(struct mc_ddr_init_param *param);
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void ddr1_init(struct mc_ddr_init_param *param);
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void ddr2_init(struct mc_ddr_init_param *param);
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void ddr_calibrate(void __iomem *memc, u32 memsize, u32 bw);
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#endif /* _MTMIPS_DDR_H_ */
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