181 lines
4.6 KiB
C
181 lines
4.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#ifndef _MTMIPS_MC_H_
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#define _MTMIPS_MC_H_
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#define MEMCTL_SDRAM_CFG0_REG 0x00
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#define DIS_CLK_GT 0x80000000
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#define CLK_SLEW_S 29
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#define CLK_SLEW_M 0x60000000
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#define TWR 0x10000000
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#define TMRD_S 24
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#define TMRD_M 0xf000000
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#define TRFC_S 20
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#define TRFC_M 0xf00000
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#define TCAS_S 16
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#define TCAS_M 0x30000
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#define TRAS_S 12
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#define TRAS_M 0xf000
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#define TRCD_S 8
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#define TRCD_M 0x300
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#define TRC_S 4
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#define TRC_M 0xf0
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#define TRP_S 0
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#define TRP_M 0x03
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#define MEMCTL_SDRAM_CFG1_REG 0x04
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#define SDRAM_INIT_START 0x80000000
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#define SDRAM_INIT_DONE 0x40000000
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#define RBC_MAPPING 0x20000000
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#define PWR_DOWN_EN 0x10000000
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#define PWR_DOWN_MODE 0x8000000
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#define SDRAM_WIDTH 0x1000000
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#define NUMCOLS_S 20
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#define NUMCOLS_M 0x300000
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#define NUMROWS_S 16
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#define NUMROWS_M 0x30000
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#define TREFR_S 0
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#define TREFR_M 0xffff
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#define MEMCTL_DDR_SELF_REFRESH_REG 0x10
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#define ODT_SRC_SEL_S 24
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#define ODT_SRC_SEL_M 0xf000000
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#define ODT_OFF_DLY_S 20
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#define ODT_OFF_DLY_M 0xf00000
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#define ODT_ON_DLY_S 16
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#define ODT_ON_DLY_M 0xf0000
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#define SR_AUTO_EN 0x10
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#define SRACK_B 0x02
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#define SRREQ_B 0x01
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#define MEMCTL_PWR_SAVE_CNT_REG 0x14
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#define PD_CNT_S 24
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#define PD_CNT_M 0xff000000
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#define SR_TAR_CNT_S 0
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#define SR_TAR_CNT_M 0xffffff
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#define MEMCTL_DLL_DBG_REG 0x20
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#define TDC_STABLE_S 12
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#define TDC_STABLE_M 0x3f000
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#define MST_DLY_SEL_S 4
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#define MST_DLY_SEL_M 0xff0
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#define CURR_STATE_S 1
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#define CURR_STATE_M 0x06
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#define ADLL_LOCK_DONE 0x01
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#define MEMCTL_DDR_CFG0_REG 0x40
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#define T_RRD_S 28
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#define T_RRD_M 0xf0000000
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#define T_RAS_S 23
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#define T_RAS_M 0xf800000
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#define T_RP_S 19
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#define T_RP_M 0x780000
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#define T_RFC_S 13
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#define T_RFC_M 0x7e000
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#define T_REFI_S 0
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#define T_REFI_M 0x1fff
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#define MEMCTL_DDR_CFG1_REG 0x44
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#define T_WTR_S 28
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#define T_WTR_M 0xf0000000
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#define T_RTP_S 24
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#define T_RTP_M 0xf000000
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#define USER_DATA_WIDTH 0x200000
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#define IND_SDRAM_SIZE_S 18
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#define IND_SDRAM_SIZE_M 0x1c0000
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#define IND_SDRAM_SIZE_8MB 1
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#define IND_SDRAM_SIZE_16MB 2
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#define IND_SDRAM_SIZE_32MB 3
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#define IND_SDRAM_SIZE_64MB 4
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#define IND_SDRAM_SIZE_128MB 5
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#define IND_SDRAM_SIZE_256MB 6
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#define IND_SDRAM_WIDTH_S 16
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#define IND_SDRAM_WIDTH_M 0x30000
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#define IND_SDRAM_WIDTH_8BIT 1
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#define IND_SDRAM_WIDTH_16BIT 2
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#define EXT_BANK_S 14
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#define EXT_BANK_M 0xc000
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#define TOTAL_SDRAM_WIDTH_S 12
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#define TOTAL_SDRAM_WIDTH_M 0x3000
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#define T_WR_S 8
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#define T_WR_M 0xf00
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#define T_MRD_S 4
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#define T_MRD_M 0xf0
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#define T_RCD_S 0
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#define T_RCD_M 0x0f
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#define MEMCTL_DDR_CFG2_REG 0x48
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#define REGE 0x80000000
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#define DDR2_MODE 0x40000000
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#define DQS0_GATING_WINDOW_S 28
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#define DQS0_GATING_WINDOW_M 0x30000000
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#define DQS1_GATING_WINDOW_S 26
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#define DQS1_GATING_WINDOW_M 0xc000000
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#define PD 0x1000
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#define WR_S 9
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#define WR_M 0xe00
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#define DLLRESET 0x100
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#define TESTMODE 0x80
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#define CAS_LATENCY_S 4
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#define CAS_LATENCY_M 0x70
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#define BURST_TYPE 0x08
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#define BURST_LENGTH_S 0
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#define BURST_LENGTH_M 0x07
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#define MEMCTL_DDR_CFG3_REG 0x4c
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#define Q_OFF 0x1000
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#define RDOS 0x800
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#define DIS_DIFF_DQS 0x400
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#define OCD_S 7
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#define OCD_M 0x380
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#define RTT1 0x40
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#define ADDITIVE_LATENCY_S 3
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#define ADDITIVE_LATENCY_M 0x38
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#define RTT0 0x04
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#define DS 0x02
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#define DLL 0x01
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#define MEMCTL_DDR_CFG4_REG 0x50
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#define FAW_S 0
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#define FAW_M 0x0f
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#define MEMCTL_DDR_DQ_DLY_REG 0x60
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#define DQ1_DELAY_SEL_S 24
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#define DQ1_DELAY_SEL_M 0xff000000
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#define DQ0_DELAY_SEL_S 16
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#define DQ0_DELAY_SEL_M 0xff0000
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#define DQ1_DELAY_COARSE_TUNING_S 12
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#define DQ1_DELAY_COARSE_TUNING_M 0xf000
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#define DQ1_DELAY_FINE_TUNING_S 8
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#define DQ1_DELAY_FINE_TUNING_M 0xf00
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#define DQ0_DELAY_COARSE_TUNING_S 4
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#define DQ0_DELAY_COARSE_TUNING_M 0xf0
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#define DQ0_DELAY_FINE_TUNING_S 0
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#define DQ0_DELAY_FINE_TUNING_M 0x0f
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#define MEMCTL_DDR_DQS_DLY_REG 0x64
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#define DQS1_DELAY_SEL_S 24
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#define DQS1_DELAY_SEL_M 0xff000000
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#define DQS0_DELAY_SEL_S 16
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#define DQS0_DELAY_SEL_M 0xff0000
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#define DQS1_DELAY_COARSE_TUNING_S 12
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#define DQS1_DELAY_COARSE_TUNING_M 0xf000
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#define DQS1_DELAY_FINE_TUNING_S 8
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#define DQS1_DELAY_FINE_TUNING_M 0xf00
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#define DQS0_DELAY_COARSE_TUNING_S 4
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#define DQS0_DELAY_COARSE_TUNING_M 0xf0
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#define DQS0_DELAY_FINE_TUNING_S 0
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#define DQS0_DELAY_FINE_TUNING_M 0x0f
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#define MEMCTL_DDR_DLL_SLV_REG 0x68
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#define DLL_SLV_UPDATE_MODE 0x100
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#define DQS_DLY_SEL_EN 0x80
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#define DQ_DLY_SEL_EN 0x01
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#endif /* _MTMIPS_MC_H_ */
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