105 lines
2.4 KiB
C
105 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#ifndef _MT7628_H_
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#define _MT7628_H_
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#define SYSCTL_BASE 0x10000000
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#define SYSCTL_SIZE 0x100
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#define MEMCTL_BASE 0x10000300
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#define MEMCTL_SIZE 0x100
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#define RBUSCTL_BASE 0x10000400
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#define RBUSCTL_SIZE 0x100
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#define RGCTL_BASE 0x10001000
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#define RGCTL_SIZE 0x800
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#define SYSCTL_EFUSE_CFG_REG 0x08
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#define EFUSE_MT7688 0x100000
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#define SYSCTL_CHIP_REV_ID_REG 0x0c
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#define PKG_ID 0x10000
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#define PKG_ID_AN 1
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#define PKG_ID_KN 0
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#define VER_S 8
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#define VER_M 0xf00
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#define ECO_S 0
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#define ECO_M 0x0f
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#define SYSCTL_SYSCFG0_REG 0x10
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#define XTAL_FREQ_SEL 0x40
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#define XTAL_40MHZ 1
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#define XTAL_25MHZ 0
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#define CHIP_MODE_S 1
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#define CHIP_MODE_M 0x0e
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#define DRAM_TYPE 0x01
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#define DRAM_DDR1 1
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#define DRAM_DDR2 0
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#define SYSCTL_ROM_STATUS_REG 0x28
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#define SYSCTL_CLKCFG0_REG 0x2c
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#define DIS_BBP_SLEEP 0x08
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#define EN_BBP_CLK 0x04
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#define CPU_PLL_FROM_BBP 0x02
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#define CPU_PLL_FROM_XTAL 0x01
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#define SYSCTL_RSTCTL_REG 0x34
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#define MC_RST 0x400
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#define SYSCTL_AGPIO_CFG_REG 0x3c
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#define EPHY_GPIO_AIO_EN_S 17
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#define EPHY_GPIO_AIO_EN_M 0x1e0000
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#define SYSCTL_GPIO_MODE1_REG 0x60
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#define UART2_MODE_S 26
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#define UART2_MODE_M 0xc000000
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#define UART1_MODE_S 24
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#define UART1_MODE_M 0x3000000
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#define UART0_MODE_S 8
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#define UART0_MODE_M 0x300
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#define SPIS_MODE_S 2
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#define SPIS_MODE_M 0x0c
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#define RBUSCTL_DYN_CFG0_REG 0x40
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#define CPU_FDIV_S 8
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#define CPU_FDIV_M 0xf00
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#define CPU_FFRAC_S 0
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#define CPU_FFRAC_M 0x0f
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#define RGCTL_PMU_G0_REG 0x100
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#define PMU_CFG_EN 0x80000000
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#define RGCTL_PMU_G1_REG 0x104
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#define RG_BUCK_FPWM 0x02
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#define RGCTL_PMU_G3_REG 0x10c
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#define NI_DDRLDO_STB 0x40000
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#define NI_DDRLDO_EN 0x10000
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#define RG_DDRLDO_VOSEL 0x40
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#define RGCTL_DDR_PAD_CK_G0_REG 0x700
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#define RGCTL_DDR_PAD_CMD_G0_REG 0x708
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#define RGCTL_DDR_PAD_DQ_G0_REG 0x710
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#define RGCTL_DDR_PAD_DQS_G0_REG 0x718
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#define RTT_S 8
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#define RTT_M 0x700
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#define RGCTL_DDR_PAD_CK_G1_REG 0x704
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#define RGCTL_DDR_PAD_CMD_G1_REG 0x70c
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#define RGCTL_DDR_PAD_DQ_G1_REG 0x714
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#define RGCTL_DDR_PAD_DQS_G1_REG 0x71c
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#define DRVP_S 0
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#define DRVP_M 0x0f
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#define DRVN_S 8
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#define DRVN_M 0xf00
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#ifndef __ASSEMBLY__
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void mt7628_ddr_init(void);
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#endif
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#endif /* _MT7628_H_ */
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