35 lines
		
	
	
		
			1.0 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			35 lines
		
	
	
		
			1.0 KiB
		
	
	
	
		
			C
		
	
	
	
| // SPDX-License-Identifier: GPL-2.0
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| /*
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|  * Copyright (C) 2020 MediaTek Inc.
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|  *
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|  * Author:  Weijie Gao <weijie.gao@mediatek.com>
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|  */
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| 
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| #include <common.h>
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| #include <asm/io.h>
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| #include "mt7628.h"
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| 
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| void mtmips_spl_serial_init(void)
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| {
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| #ifdef CONFIG_SPL_SERIAL_SUPPORT
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| 	void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
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| 
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| #if CONFIG_CONS_INDEX == 1
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| 	clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART0_MODE_M);
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| #elif CONFIG_CONS_INDEX == 2
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| 	clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART1_MODE_M);
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| #elif CONFIG_CONS_INDEX == 3
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| 	setbits_32(base + SYSCTL_AGPIO_CFG_REG, EPHY_GPIO_AIO_EN_M);
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| #ifdef CONFIG_SPL_UART2_SPIS_PINMUX
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| 	setbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M);
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| 	clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M,
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| 		      1 << UART2_MODE_S);
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| #else
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| 	clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M);
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| 	clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M,
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| 		      1 << SPIS_MODE_S);
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| #endif /* CONFIG_SPL_UART2_SPIS_PINMUX */
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| #endif /* CONFIG_CONS_INDEX */
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| #endif /* CONFIG_SPL_SERIAL_SUPPORT */
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| }
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