140 lines
		
	
	
		
			2.6 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
			
		
		
	
	
			140 lines
		
	
	
		
			2.6 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
| // SPDX-License-Identifier: GPL-2.0+
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| /*
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|  * Hitachi Power Grids SUPC5 Device Tree Source
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|  *
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|  * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
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|  *
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|  */
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| 
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| /dts-v1/;
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| 
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| #include "km8321.dtsi"
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| 
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| / {
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| 	model = "SUPC5";
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| 	compatible = "hitachi,kmpbec8321";
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| 	#address-cells = <1>;
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| 	#size-cells = <1>;
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| 
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| 	aliases {
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| 		ethernet0 = &enet_piggy2;
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| 		serial0 = &serial0;
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| 	};
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| };
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| 
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| &i2c0 {
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| 	mux@70 {
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| 		compatible = "nxp,pca9547";
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| 		reg = <0x70>;
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| 		#address-cells = <1>;
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| 		#size-cells = <0>;
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| 
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| 		i2c@1 {
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| 			reg = <1>;
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| 			#address-cells = <1>;
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| 			#size-cells = <0>;
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| 
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| 			/* Inventory EEPROM of the unit itself */
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| 			ivm@50 {
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| 				label = "MAIN_CTRL";
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| 				compatible = "dummy";
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| 				reg = <0x50>;
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| 			};
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| 		};
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| 
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| 		i2c@2 {
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| 			reg = <2>;
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| 			#address-cells = <1>;
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| 			#size-cells = <0>;
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| 
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| 			/* Temperature sensors */
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| 			temp@49 {
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| 				label = "board";
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| 				compatible = "national,lm75";
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| 				reg = <0x49>;
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| 			};
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| 		};
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| 	};
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| };
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| 
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| &par_io {
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| 	/* UCC5 as HDLC controller for ICN */
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| 	pio_ucc5: ucc_pin@04 {
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| 		pio-map = <
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| 			/* port pin dir open_drain assignment has_irq */
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| 			2   0  1  0  2  0	/* TxD0 */
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| 			2   8  2  0  2  0	/* RxD0 */
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| 			2  29  2  0  2  0	/* CTS */
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| 			3  30  2  0  1  0	/* ICN CLK */
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| 			>;
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| 	};
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| 
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| 	/* UCC4 Piggy Ethernet */
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| 	pio_ucc4: ucc_pin@03 {
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| 		pio-map = <
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| 			/* port pin dir open_drain assignment has_irq */
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| 			3   4  3  0  2  0	/* MDIO */
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| 			3   5  1  0  2  0	/* MDC  */
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| 
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| 			1 18  1  0  1  0	/* TxD0 */
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| 			1 19  1  0  1  0	/* TxD1 */
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| 			1 22  2  0  1  0	/* RxD0 */
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| 			1 23  2  0  1  0	/* RxD1 */
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| 			1 26  2  0  1  0	/* RX_ER */
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| 			1 28  2  0  1  0	/* RX_DV */
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| 			1 30  1  0  1  0	/* TX_EN */
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| 			1 31  2  0  1  0	/* CRS */
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| 			/* UCC4_RMII_CLK (CLK17) */
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| 			3 10  2  0  3  0
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| 		>;
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| 	};
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| 
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| 	pio_spi: spi_pin@01 {
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| 		pio-map = <
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| 			/*
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| 			 * port  pin  dir  open_drain  assignment  has_irq
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| 			 * SPI_MOSI (PD0, bi, f3)
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| 			 */
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| 			3  0  3  0  1  0
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| 			/* SPI_MISO (PD1, bi, f3) */
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| 			3  1  3  0  1  0
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| 			/* SPI_CLK  (PD2, bi, f3) */
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| 			3  2  3  0  1  0
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| 		>;
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| 	};
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| };
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| 
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| &spi0 {
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| 	pio-handle = <&pio_spi>;
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| };
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| 
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| &localbus {
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| 	ranges = <0 0 0xf0000000 0x04000000     /* LB 0 Flash (boot) */
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| 		  1 0 0xe8000000 0x01000000     /* LB 1 PRIO1 and Piggy */
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| 		  2 0 0xa0000000 0x10000000>;   /* LB 2 LPXF */
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| 
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| 	flash@0,0 {
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| 		compatible = "cfi-flash";
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| 		reg = <0 0x00000000 0x04000000>;
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| 		bank-width = <2>;
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| 		#address-cells = <1>;
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| 		#size-cells = <1>;
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| 		partition@0 { /* 768KB */
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| 			label = "u-boot";
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| 			reg = <0 0xC0000>;
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| 		};
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| 		partition@c0000 { /* 128KB */
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| 			label = "env";
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| 			reg = <0xc0000 0x20000>;
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| 		};
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| 		partition@e0000 { /* 128KB */
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| 			label = "envred";
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| 			reg = <0xe0000 0x20000>;
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| 		};
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| 		partition@100000 { /* 64512KB */
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| 			label = "ubi0";
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| 			reg = <0x100000 0x3F00000>;
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| 		};
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| 	};
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| };
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