115 lines
1.9 KiB
Plaintext
115 lines
1.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* T2080RDB Device Tree Source
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*
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* Copyright 2013 - 2015 Freescale Semiconductor Inc.
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* Copyright 2019-2021 NXP
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*/
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/include/ "t2080.dtsi"
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/ {
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model = "fsl,T2080RDB";
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compatible = "fsl,T2080RDB";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases {
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spi0 = &espi0;
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};
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};
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&soc {
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fman@400000 {
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ethernet@e0000 {
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phy-handle = <&xg_aq1202_phy3>;
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phy-connection-type = "xgmii";
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};
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ethernet@e2000 {
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phy-handle = <&xg_aq1202_phy4>;
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phy-connection-type = "xgmii";
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};
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ethernet@e4000 {
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phy-handle = <&rgmii_phy1>;
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phy-connection-type = "rgmii";
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};
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ethernet@e6000 {
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phy-handle = <&rgmii_phy2>;
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phy-connection-type = "rgmii";
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};
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ethernet@f0000 {
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phy-handle = <&xg_cs4315_phy2>;
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phy-connection-type = "xgmii";
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};
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ethernet@f2000 {
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phy-handle = <&xg_cs4315_phy1>;
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phy-connection-type = "xgmii";
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};
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mdio@fc000 {
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rgmii_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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rgmii_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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};
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mdio@fd000 {
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xg_cs4315_phy1: ethernet-phy@c {
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compatible = "ethernet-phy-id13e5.1002";
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reg = <0xc>;
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};
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xg_cs4315_phy2: ethernet-phy@d {
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compatible = "ethernet-phy-id13e5.1002";
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reg = <0xd>;
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};
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xg_aq1202_phy3: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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};
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#ifdef CONFIG_T2080RDB_REV_D
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xg_aq1202_phy4: ethernet-phy@8 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x8>;
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};
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#else
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xg_aq1202_phy4: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x1>;
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};
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#endif
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};
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};
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};
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&espi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor"; /* 16MB */
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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spi-max-frequency = <10000000>; /* input clock */
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};
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};
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&i2c0 {
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status = "okay";
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rtc@68 {
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compatible = "dallas,ds1339";
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reg = <0x68>;
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};
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};
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/include/ "t2080si-post.dtsi"
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