396 lines
10 KiB
C
396 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 Google LLC
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* Copyright (C) 2015 - 2017 Intel Corp.
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* Copyright (C) 2017 - 2019 Siemens AG
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
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*
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* Portions from coreboot soc/intel/apollolake/chip.c
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*/
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#define LOG_CATEGORY UCLASS_NORTHBRIDGE
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#include <common.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <log.h>
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#include <spl.h>
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#include <tables_csum.h>
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#include <acpi/acpi_table.h>
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#include <asm/acpi_nhlt.h>
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#include <asm/intel_pinctrl.h>
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#include <asm/intel_regs.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/arch/acpi.h>
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#include <asm/arch/hostbridge.h>
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#include <asm/arch/systemagent.h>
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#include <dt-bindings/sound/nhlt.h>
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#include <dm/acpi.h>
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enum {
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PCIEXBAR = 0x60,
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PCIEXBAR_LENGTH_256MB = 0,
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PCIEXBAR_LENGTH_128MB,
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PCIEXBAR_LENGTH_64MB,
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PCIEXBAR_PCIEXBAREN = 1 << 0,
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BGSM = 0xb4, /* Base GTT Stolen Memory */
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TSEG = 0xb8, /* TSEG base */
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TOLUD = 0xbc,
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};
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#if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)
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static const struct nhlt_format_config dmic_1ch_formats[] = {
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/* 48 KHz 16-bits per sample. */
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{
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.num_channels = 1,
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.sample_freq_khz = 48,
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.container_bits_per_sample = 16,
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.valid_bits_per_sample = 16,
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.settings_file = "dmic-1ch-48khz-16b.dat",
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},
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};
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static const struct nhlt_dmic_array_config dmic_1ch_mic_config = {
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.tdm_config = {
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.config_type = NHLT_TDM_MIC_ARRAY,
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},
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.array_type = NHLT_MIC_ARRAY_VENDOR_DEFINED,
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};
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static const struct nhlt_endp_descriptor dmic_1ch_descriptors[] = {
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{
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.link = NHLT_LINK_PDM,
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.device = NHLT_PDM_DEV,
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.direction = NHLT_DIR_CAPTURE,
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.vid = NHLT_VID,
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.did = NHLT_DID_DMIC,
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.cfg = &dmic_1ch_mic_config,
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.cfg_size = sizeof(dmic_1ch_mic_config),
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.formats = dmic_1ch_formats,
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.num_formats = ARRAY_SIZE(dmic_1ch_formats),
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},
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};
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static const struct nhlt_format_config dmic_2ch_formats[] = {
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/* 48 KHz 16-bits per sample. */
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{
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.num_channels = 2,
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.sample_freq_khz = 48,
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.container_bits_per_sample = 16,
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.valid_bits_per_sample = 16,
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.settings_file = "dmic-2ch-48khz-16b.dat",
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},
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};
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static const struct nhlt_dmic_array_config dmic_2ch_mic_config = {
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.tdm_config = {
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.config_type = NHLT_TDM_MIC_ARRAY,
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},
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.array_type = NHLT_MIC_ARRAY_2CH_SMALL,
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};
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static const struct nhlt_endp_descriptor dmic_2ch_descriptors[] = {
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{
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.link = NHLT_LINK_PDM,
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.device = NHLT_PDM_DEV,
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.direction = NHLT_DIR_CAPTURE,
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.vid = NHLT_VID,
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.did = NHLT_DID_DMIC,
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.cfg = &dmic_2ch_mic_config,
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.cfg_size = sizeof(dmic_2ch_mic_config),
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.formats = dmic_2ch_formats,
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.num_formats = ARRAY_SIZE(dmic_2ch_formats),
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},
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};
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static const struct nhlt_format_config dmic_4ch_formats[] = {
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/* 48 KHz 16-bits per sample. */
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{
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.num_channels = 4,
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.sample_freq_khz = 48,
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.container_bits_per_sample = 16,
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.valid_bits_per_sample = 16,
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.settings_file = "dmic-4ch-48khz-16b.dat",
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},
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};
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static const struct nhlt_dmic_array_config dmic_4ch_mic_config = {
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.tdm_config = {
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.config_type = NHLT_TDM_MIC_ARRAY,
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},
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.array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED,
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};
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static const struct nhlt_endp_descriptor dmic_4ch_descriptors[] = {
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{
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.link = NHLT_LINK_PDM,
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.device = NHLT_PDM_DEV,
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.direction = NHLT_DIR_CAPTURE,
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.vid = NHLT_VID,
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.did = NHLT_DID_DMIC,
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.cfg = &dmic_4ch_mic_config,
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.cfg_size = sizeof(dmic_4ch_mic_config),
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.formats = dmic_4ch_formats,
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.num_formats = ARRAY_SIZE(dmic_4ch_formats),
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},
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};
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#endif
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static int apl_hostbridge_early_init_pinctrl(struct udevice *dev)
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{
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struct apl_hostbridge_plat *plat = dev_get_plat(dev);
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struct udevice *pinctrl;
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int ret;
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ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl);
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if (ret)
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return log_msg_ret("no hostbridge pinctrl", ret);
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return pinctrl_config_pads(pinctrl, plat->early_pads,
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plat->early_pads_count);
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}
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static int apl_hostbridge_early_init(struct udevice *dev)
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{
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struct apl_hostbridge_plat *plat = dev_get_plat(dev);
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u32 region_size;
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ulong base;
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u32 reg;
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int ret;
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/* Set up the MCHBAR */
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pci_x86_read_config(plat->bdf, MCHBAR, &base, PCI_SIZE_32);
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base = MCH_BASE_ADDRESS;
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pci_x86_write_config(plat->bdf, MCHBAR, base | 1, PCI_SIZE_32);
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/*
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* The PCIEXBAR is assumed to live in the memory mapped IO space under
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* 4GiB
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*/
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pci_x86_write_config(plat->bdf, PCIEXBAR + 4, 0, PCI_SIZE_32);
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switch (plat->pciex_region_size >> 20) {
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default:
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case 256:
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region_size = PCIEXBAR_LENGTH_256MB;
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break;
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case 128:
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region_size = PCIEXBAR_LENGTH_128MB;
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break;
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case 64:
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region_size = PCIEXBAR_LENGTH_64MB;
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break;
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}
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reg = CONFIG_MMCONF_BASE_ADDRESS | (region_size << 1)
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| PCIEXBAR_PCIEXBAREN;
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pci_x86_write_config(plat->bdf, PCIEXBAR, reg, PCI_SIZE_32);
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/*
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* TSEG defines the base of SMM range. BIOS determines the base
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* of TSEG memory which must be at or below Graphics base of GTT
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* Stolen memory, hence its better to clear TSEG register early
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* to avoid power on default non-zero value (if any).
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*/
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pci_x86_write_config(plat->bdf, TSEG, 0, PCI_SIZE_32);
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ret = apl_hostbridge_early_init_pinctrl(dev);
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if (ret)
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return log_msg_ret("pinctrl", ret);
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return 0;
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}
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static int apl_hostbridge_of_to_plat(struct udevice *dev)
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{
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struct apl_hostbridge_plat *plat = dev_get_plat(dev);
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struct udevice *pinctrl;
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int ret;
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/*
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* The host bridge holds the early pad data needed to get through TPL.
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* This is a small amount of data, enough to fit in TPL, so we keep it
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* separate from the full pad data, stored in the fsp-s subnode. That
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* subnode is not present in TPL, to save space.
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*/
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ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl);
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if (ret)
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return log_msg_ret("no hostbridge PINCTRL", ret);
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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int root;
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/* Get length of PCI Express Region */
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plat->pciex_region_size = dev_read_u32_default(dev, "pciex-region-size",
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256 << 20);
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root = pci_get_devfn(dev);
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if (root < 0)
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return log_msg_ret("Cannot get host-bridge PCI address", root);
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plat->bdf = root;
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ret = pinctrl_read_pads(pinctrl, dev_ofnode(dev), "early-pads",
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&plat->early_pads, &plat->early_pads_count);
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if (ret)
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return log_msg_ret("early-pads", ret);
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#else
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struct dtd_intel_apl_hostbridge *dtplat = &plat->dtplat;
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int size;
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plat->pciex_region_size = dtplat->pciex_region_size;
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plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]);
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/* Assume that if everything is 0, it is empty */
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plat->early_pads = dtplat->early_pads;
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size = ARRAY_SIZE(dtplat->early_pads);
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plat->early_pads_count = pinctrl_count_pads(pinctrl, plat->early_pads,
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size);
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#endif
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return 0;
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}
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static int apl_hostbridge_probe(struct udevice *dev)
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{
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if (spl_phase() == PHASE_TPL)
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return apl_hostbridge_early_init(dev);
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return 0;
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}
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static int apl_acpi_hb_get_name(const struct udevice *dev, char *out_name)
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{
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return acpi_copy_name(out_name, "RHUB");
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}
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#if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)
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static int apl_acpi_hb_write_tables(const struct udevice *dev,
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struct acpi_ctx *ctx)
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{
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struct acpi_table_header *header;
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struct acpi_dmar *dmar;
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u32 val;
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/*
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* Create DMAR table only if virtualization is enabled. Due to some
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* constraints on Apollo Lake SoC (some stepping affected), VTD could
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* not be enabled together with IPU. Doing so will override and disable
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* VTD while leaving CAPID0_A still reporting that VTD is available.
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* As in this case FSP will lock VTD to disabled state, we need to make
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* sure that DMAR table generation only happens when at least DEFVTBAR
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* is enabled. Otherwise the DMAR header will be generated while the
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* content of the table will be missing.
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*/
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dm_pci_read_config32(dev, CAPID0_A, &val);
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if ((val & VTD_DISABLE) ||
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!(readl(MCHBAR_REG(DEFVTBAR)) & VTBAR_ENABLED))
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return 0;
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log_debug("ACPI: * DMAR\n");
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dmar = (struct acpi_dmar *)ctx->current;
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header = &dmar->header;
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acpi_create_dmar(dmar, DMAR_INTR_REMAP);
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ctx->current += sizeof(struct acpi_dmar);
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apl_acpi_fill_dmar(ctx);
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/* (Re)calculate length and checksum */
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header->length = ctx->current - (void *)dmar;
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header->checksum = table_compute_checksum((void *)dmar, header->length);
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acpi_align(ctx);
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acpi_add_table(ctx, dmar);
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return 0;
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}
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static int apl_acpi_setup_nhlt(const struct udevice *dev, struct acpi_ctx *ctx)
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{
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struct nhlt *nhlt = ctx->nhlt;
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u32 channels;
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ofnode node;
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node = ofnode_find_subnode(dev_ofnode(dev), "nhlt");
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if (ofnode_read_u32(node, "intel,dmic-channels", &channels))
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return log_msg_ret("channels", -EINVAL);
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switch (channels) {
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case 1:
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return nhlt_add_endpoints(nhlt, dmic_1ch_descriptors,
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ARRAY_SIZE(dmic_1ch_descriptors));
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case 2:
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return nhlt_add_endpoints(nhlt, dmic_2ch_descriptors,
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ARRAY_SIZE(dmic_2ch_descriptors));
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case 4:
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return nhlt_add_endpoints(nhlt, dmic_4ch_descriptors,
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ARRAY_SIZE(dmic_4ch_descriptors));
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}
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return log_msg_ret("channels", -EINVAL);
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}
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#endif
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static int apl_hostbridge_remove(struct udevice *dev)
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{
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/*
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* TODO(sjg@chromium.org): Consider adding code from coreboot's
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* platform_fsp_notify_status()
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*/
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return 0;
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}
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static ulong sa_read_reg(struct udevice *dev, int reg)
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{
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u32 val;
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/* All regions concerned for have 1 MiB alignment */
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dm_pci_read_config32(dev, BGSM, &val);
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return ALIGN_DOWN(val, 1 << 20);
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}
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ulong sa_get_tolud_base(struct udevice *dev)
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{
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return sa_read_reg(dev, TOLUD);
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}
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ulong sa_get_gsm_base(struct udevice *dev)
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{
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return sa_read_reg(dev, BGSM);
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}
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ulong sa_get_tseg_base(struct udevice *dev)
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{
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return sa_read_reg(dev, TSEG);
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}
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struct acpi_ops apl_hostbridge_acpi_ops = {
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.get_name = apl_acpi_hb_get_name,
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#if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)
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.write_tables = apl_acpi_hb_write_tables,
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.setup_nhlt = apl_acpi_setup_nhlt,
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#endif
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};
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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static const struct udevice_id apl_hostbridge_ids[] = {
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{ .compatible = "intel,apl-hostbridge" },
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{ }
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};
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#endif
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U_BOOT_DRIVER(intel_apl_hostbridge) = {
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.name = "intel_apl_hostbridge",
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.id = UCLASS_NORTHBRIDGE,
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.of_match = of_match_ptr(apl_hostbridge_ids),
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.of_to_plat = apl_hostbridge_of_to_plat,
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.probe = apl_hostbridge_probe,
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.remove = apl_hostbridge_remove,
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.plat_auto = sizeof(struct apl_hostbridge_plat),
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ACPI_OPS_PTR(&apl_hostbridge_acpi_ops)
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.flags = DM_FLAG_OS_PREPARE,
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};
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