145 lines
3.5 KiB
C
145 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 Google LLC
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*
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* From coreboot Apollo Lake support lpc.c
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <spl.h>
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#include <acpi/acpi_table.h>
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#include <asm/cpu_common.h>
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#include <asm/intel_acpi.h>
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#include <asm/lpc_common.h>
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#include <asm/pci.h>
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#include <asm/arch/iomap.h>
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#include <asm/arch/lpc.h>
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#include <dm/acpi.h>
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#include <linux/log2.h>
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void lpc_enable_fixed_io_ranges(uint io_enables)
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{
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pci_x86_clrset_config(PCH_DEV_LPC, LPC_IO_ENABLES, 0, io_enables,
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PCI_SIZE_16);
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}
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/*
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* Find the first unused IO window.
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* Returns -1 if not found, 0 for reg 0x84, 1 for reg 0x88 ...
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*/
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static int find_unused_pmio_window(void)
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{
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int i;
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ulong lgir;
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for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
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pci_x86_read_config(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i),
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&lgir, PCI_SIZE_32);
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if (!(lgir & LPC_LGIR_EN))
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return i;
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}
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return -1;
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}
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int lpc_open_pmio_window(uint base, uint size)
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{
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int i, lgir_reg_num;
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u32 lgir_reg_offset, lgir, window_size, alignment;
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ulong bridged_size, bridge_base;
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ulong reg;
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log_debug("LPC: Trying to open IO window from %x size %x\n", base,
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size);
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bridged_size = 0;
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bridge_base = base;
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while (bridged_size < size) {
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/* Each IO range register can only open a 256-byte window */
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window_size = min(size, (uint)LPC_LGIR_MAX_WINDOW_SIZE);
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/* Window size must be a power of two for the AMASK to work */
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alignment = 1UL << (order_base_2(window_size));
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window_size = ALIGN(window_size, alignment);
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/* Address[15:2] in LGIR[15:12] and Mask[7:2] in LGIR[23:18] */
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lgir = (bridge_base & LPC_LGIR_ADDR_MASK) | LPC_LGIR_EN;
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lgir |= ((window_size - 1) << 16) & LPC_LGIR_AMASK_MASK;
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/* Skip programming if same range already programmed */
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for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
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pci_x86_read_config(PCH_DEV_LPC,
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LPC_GENERIC_IO_RANGE(i), ®,
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PCI_SIZE_32);
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if (lgir == reg)
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return -EALREADY;
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}
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lgir_reg_num = find_unused_pmio_window();
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if (lgir_reg_num < 0) {
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if (spl_phase() > PHASE_TPL) {
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log_err("LPC: Cannot open IO window: %lx size %lx\n",
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bridge_base, size - bridged_size);
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log_err("No more IO windows\n");
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}
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return -ENOSPC;
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}
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lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num);
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pci_x86_write_config(PCH_DEV_LPC, lgir_reg_offset, lgir,
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PCI_SIZE_32);
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log_debug("LPC: Opened IO window LGIR%d: base %lx size %x\n",
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lgir_reg_num, bridge_base, window_size);
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bridged_size += window_size;
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bridge_base += window_size;
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}
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return 0;
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}
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void lpc_io_setup_comm_a_b(void)
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{
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/* ComA Range 3F8h-3FFh [2:0] */
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u16 com_ranges = LPC_IOD_COMA_RANGE;
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u16 com_enable = LPC_IOE_COMA_EN;
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/* Setup I/O Decode Range Register for LPC */
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pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, com_ranges);
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/* Enable ComA and ComB Port */
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lpc_enable_fixed_io_ranges(com_enable);
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}
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static int apl_acpi_lpc_get_name(const struct udevice *dev, char *out_name)
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{
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return acpi_copy_name(out_name, "LPCB");
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}
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struct acpi_ops apl_lpc_acpi_ops = {
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.get_name = apl_acpi_lpc_get_name,
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#ifdef CONFIG_GENERATE_ACPI_TABLE
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.write_tables = intel_southbridge_write_acpi_tables,
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#endif
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.inject_dsdt = southbridge_inject_dsdt,
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};
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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static const struct udevice_id apl_lpc_ids[] = {
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{ .compatible = "intel,apl-lpc" },
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{ }
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};
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#endif
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/* All pads are LPC already configured by the hostbridge, so no probing here */
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U_BOOT_DRIVER(intel_apl_lpc) = {
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.name = "intel_apl_lpc",
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.id = UCLASS_LPC,
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.of_match = of_match_ptr(apl_lpc_ids),
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ACPI_OPS_PTR(&apl_lpc_acpi_ops)
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};
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