68 lines
1.3 KiB
C
68 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 NXP
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/imx8ulp-pins.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/pcc.h>
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#include <asm/arch/sys_proto.h>
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#include <miiphy.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if IS_ENABLED(CONFIG_FEC_MXC)
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#define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_UP | PAD_CTL_DSE | PAD_CTL_IBE_ENABLE)
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static iomux_cfg_t const enet_clk_pads[] = {
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IMX8ULP_PAD_PTE19__ENET0_REFCLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
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IMX8ULP_PAD_PTF10__ENET0_1588_CLKIN | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
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};
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static int setup_fec(void)
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{
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/*
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* Since ref clock and timestamp clock are from external,
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* set the iomux prior the clock enablement
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*/
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imx8ulp_iomux_setup_multiple_pads(enet_clk_pads, ARRAY_SIZE(enet_clk_pads));
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/* Select enet time stamp clock: 001 - External Timestamp Clock */
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cgc1_enet_stamp_sel(1);
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/* enable FEC PCC */
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pcc_clock_enable(4, ENET_PCC4_SLOT, true);
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pcc_reset_peripheral(4, ENET_PCC4_SLOT, false);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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int board_init(void)
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{
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if (IS_ENABLED(CONFIG_FEC_MXC))
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setup_fec();
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return 0;
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}
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int board_early_init_f(void)
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{
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return 0;
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}
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int board_late_init(void)
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{
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return 0;
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}
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