204 lines
3.6 KiB
C
204 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017-2018 NXP
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*/
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#include <common.h>
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#include <fdt_support.h>
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#include <i2c.h>
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#include <asm/cache.h>
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#include <init.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#ifdef CONFIG_FSL_LS_PPA
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#include <asm/arch/ppa.h>
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#endif
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#include <asm/arch/mmu.h>
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#include <asm/arch/soc.h>
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#include <fsl_esdhc.h>
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#include <hwconfig.h>
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#include <env_internal.h>
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#include <fsl_mmdc.h>
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#include <netdev.h>
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#include <fsl_sec.h>
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#include <net/pfe_eth/pfe/pfe_hw.h>
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DECLARE_GLOBAL_DATA_PTR;
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static inline int get_board_version(void)
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{
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uint32_t val;
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#ifdef CONFIG_TARGET_LS1012AFRDM
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val = 0;
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#else
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struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
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val = in_be32(&pgpio->gpdat) & BOARD_REV_MASK;/*Get GPIO2 11,12,14*/
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#endif
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return val;
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}
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int checkboard(void)
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{
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#ifdef CONFIG_TARGET_LS1012AFRDM
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puts("Board: LS1012AFRDM ");
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#else
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int rev;
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rev = get_board_version();
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puts("Board: FRWY-LS1012A ");
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puts("Version");
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switch (rev) {
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case BOARD_REV_A_B:
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puts(": RevA/B ");
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break;
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case BOARD_REV_C:
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puts(": RevC ");
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break;
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default:
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puts(": unknown");
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break;
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}
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#endif
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return 0;
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}
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#ifdef CONFIG_TARGET_LS1012AFRWY
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int esdhc_status_fixup(void *blob, const char *compat)
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{
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char esdhc0_path[] = "/soc/esdhc@1560000";
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char esdhc1_path[] = "/soc/esdhc@1580000";
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do_fixup_by_path(blob, esdhc0_path, "status", "okay",
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sizeof("okay"), 1);
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do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
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sizeof("disabled"), 1);
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return 0;
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}
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#endif
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#ifdef CONFIG_TFABOOT
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int dram_init(void)
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{
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#ifdef CONFIG_TARGET_LS1012AFRWY
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int board_rev;
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#endif
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gd->ram_size = tfa_get_dram_size();
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if (!gd->ram_size) {
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#ifdef CONFIG_TARGET_LS1012AFRWY
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board_rev = get_board_version();
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if (board_rev & BOARD_REV_C)
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gd->ram_size = SYS_SDRAM_SIZE_1024;
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else
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gd->ram_size = SYS_SDRAM_SIZE_512;
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#else
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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#endif
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}
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return 0;
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}
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#else
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int dram_init(void)
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{
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#ifdef CONFIG_TARGET_LS1012AFRWY
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int board_rev;
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#endif
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struct fsl_mmdc_info mparam = {
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0x04180000, /* mdctl */
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0x00030035, /* mdpdc */
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0x12554000, /* mdotc */
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0xbabf7954, /* mdcfg0 */
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0xdb328f64, /* mdcfg1 */
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0x01ff00db, /* mdcfg2 */
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0x00001680, /* mdmisc */
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0x0f3c8000, /* mdref */
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0x00002000, /* mdrwd */
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0x00bf1023, /* mdor */
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0x0000003f, /* mdasp */
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0x0000022a, /* mpodtctrl */
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0xa1390003, /* mpzqhwctrl */
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};
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#ifdef CONFIG_TARGET_LS1012AFRWY
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board_rev = get_board_version();
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if (board_rev == BOARD_REV_C) {
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mparam.mdctl = 0x05180000;
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gd->ram_size = SYS_SDRAM_SIZE_1024;
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} else {
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gd->ram_size = SYS_SDRAM_SIZE_512;
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}
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#else
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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#endif
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mmdc_init(&mparam);
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#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
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/* This will break-before-make MMU for DDR */
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update_early_mmu_table();
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#endif
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return 0;
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}
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#endif
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int board_early_init_f(void)
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{
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fsl_lsch2_early_init_f();
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return 0;
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}
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int board_init(void)
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
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CONFIG_SYS_CCI400_OFFSET);
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/*
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* Set CCI-400 control override register to enable barrier
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* transaction
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*/
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if (current_el() == 3)
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
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#ifdef CONFIG_ENV_IS_NOWHERE
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gd->env_addr = (ulong)&default_environment[0];
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#endif
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#ifdef CONFIG_FSL_CAAM
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sec_init();
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#endif
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#ifdef CONFIG_FSL_LS_PPA
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ppa_init();
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#endif
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return 0;
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}
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#ifdef CONFIG_FSL_PFE
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void board_quiesce_devices(void)
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{
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pfe_command_stop(0, NULL);
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}
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#endif
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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arch_fixup_fdt(blob);
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ft_cpu_setup(blob, bd);
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return 0;
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}
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