126 lines
		
	
	
		
			2.7 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			126 lines
		
	
	
		
			2.7 KiB
		
	
	
	
		
			C
		
	
	
	
| // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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| /*
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|  * Copyright (c) 2018 Microsemi Corporation
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|  */
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| 
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| #include <common.h>
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| #include <image.h>
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| #include <init.h>
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| #include <log.h>
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| #include <asm/global_data.h>
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| #include <asm/io.h>
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| #include <asm/addrspace.h>
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| #include <asm/types.h>
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| #include <spi.h>
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| #include <led.h>
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| #include <wait_bit.h>
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| #include <miiphy.h>
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| #include <linux/bitops.h>
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| 
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| DECLARE_GLOBAL_DATA_PTR;
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| 
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| enum {
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| 	BOARD_TYPE_PCB120 = 0xAABBCC00,
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| 	BOARD_TYPE_PCB123,
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| };
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| 
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| void mscc_switch_reset(bool enter)
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| {
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| 	/* Nasty workaround to avoid GPIO19 (DDR!) being reset */
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| 	mscc_gpio_set_alternate(19, 2);
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| 
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| 	debug("applying SwC reset\n");
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| 
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| 	writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
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| 	writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
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| 
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| 	if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST,
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| 			      PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false))
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| 		pr_err("Tiemout while waiting for switch reset\n");
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| 
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| 	/*
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| 	 * Reset GPIO19 mode back as regular GPIO, output, high (DDR
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| 	 * not reset) (Order is important)
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| 	 */
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| 	setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
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| 	writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
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| 	mscc_gpio_set_alternate(19, 0);
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| }
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| 
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| int board_phy_config(struct phy_device *phydev)
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| {
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| 	if (gd->board_type == BOARD_TYPE_PCB123)
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| 		return 0;
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| 
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| 	phy_write(phydev, 0, 31, 0x10);
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| 	phy_write(phydev, 0, 18, 0x80F0);
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| 	while (phy_read(phydev, 0, 18) & 0x8000)
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| 		;
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| 	phy_write(phydev, 0, 31, 0);
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| 
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| 	return 0;
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| }
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| 
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| void board_debug_uart_init(void)
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| {
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| 	/* too early for the pinctrl driver, so configure the UART pins here */
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| 	mscc_gpio_set_alternate(6, 1);
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| 	mscc_gpio_set_alternate(7, 1);
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| }
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| 
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| int board_early_init_r(void)
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| {
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| 	/* Prepare SPI controller to be used in master mode */
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| 	writel(0, BASE_CFG + ICPU_SW_MODE);
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| 	clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
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| 			ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
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| 			ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
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| 
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| 	/* Address of boot parameters */
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| 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
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| 
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| 	/* LED setup */
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| 	if (IS_ENABLED(CONFIG_LED))
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| 		led_default_state();
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| 
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| 	return 0;
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| }
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| 
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| static void do_board_detect(void)
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| {
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| 	u16 dummy = 0;
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| 
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| 	/* Enable MIIM */
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| 	mscc_gpio_set_alternate(14, 1);
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| 	mscc_gpio_set_alternate(15, 1);
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| 	if (mscc_phy_rd(1, 0, 0, &dummy) == 0)
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| 		gd->board_type = BOARD_TYPE_PCB120;
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| 	else
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| 		gd->board_type = BOARD_TYPE_PCB123;
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| }
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| 
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| #if defined(CONFIG_MULTI_DTB_FIT)
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| int board_fit_config_name_match(const char *name)
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| {
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| 	if (gd->board_type == BOARD_TYPE_PCB120 &&
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| 	    strcmp(name, "ocelot_pcb120") == 0)
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| 		return 0;
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| 
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| 	if (gd->board_type == BOARD_TYPE_PCB123 &&
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| 	    strcmp(name, "ocelot_pcb123") == 0)
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| 		return 0;
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| 
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| 	return -1;
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| }
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| #endif
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| 
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| #if defined(CONFIG_DTB_RESELECT)
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| int embedded_dtb_select(void)
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| {
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| 	do_board_detect();
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| 	fdtdec_setup();
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| 
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| 	return 0;
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| }
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| #endif
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