139 lines
3.4 KiB
C
139 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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* Roy Zang <tie-fei.zang@freescale.com>
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*/
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#include <common.h>
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#include <env.h>
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#include <phy.h>
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#include <fm_eth.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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#include <hwconfig.h>
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u32 port_to_devdisr[] = {
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[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
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[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
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[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
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[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
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[FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
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[FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
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[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
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[FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
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};
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static int is_device_disabled(enum fm_port port)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 devdisr2 = in_be32(&gur->devdisr2);
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return port_to_devdisr[port] & devdisr2;
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}
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void fman_disable_port(enum fm_port port)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
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}
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void fman_enable_port(enum fm_port port)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
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}
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phy_interface_t fman_port_enet_if(enum fm_port port)
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{
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#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
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u32 serdes2_prtcl;
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char buffer[HWCONFIG_BUFFER_SIZE];
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char *buf = NULL;
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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#endif
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if (is_device_disabled(port))
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return PHY_INTERFACE_MODE_NONE;
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/*B4860 has two 10Gig Mac*/
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if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
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((is_serdes_configured(XAUI_FM1_MAC9)) ||
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#if (!defined(CONFIG_TARGET_B4860QDS) && \
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!defined(CONFIG_TARGET_B4R420QDS))
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(is_serdes_configured(XFI_FM1_MAC9)) ||
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(is_serdes_configured(XFI_FM1_MAC10)) ||
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#endif
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(is_serdes_configured(XAUI_FM1_MAC10))
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))
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return PHY_INTERFACE_MODE_XGMII;
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#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
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serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
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if (serdes2_prtcl) {
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serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
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switch (serdes2_prtcl) {
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case 0x80:
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case 0x81:
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case 0x82:
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case 0x83:
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case 0x84:
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case 0x85:
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case 0x86:
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case 0x87:
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case 0x88:
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case 0x89:
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case 0x8a:
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case 0x8b:
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case 0x8c:
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case 0x8d:
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case 0x8e:
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case 0xb1:
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case 0xb2:
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/*
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* Extract hwconfig from environment since environment
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* is not setup yet
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*/
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env_get_f("hwconfig", buffer, sizeof(buffer));
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buf = buffer;
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/* check if XFI interface enable in hwconfig for 10g */
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if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
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"sfp_amc", "sfp", buf)) {
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if ((port == FM1_10GEC1 ||
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port == FM1_10GEC2) &&
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((is_serdes_configured(XFI_FM1_MAC9)) ||
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(is_serdes_configured(XFI_FM1_MAC10))))
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return PHY_INTERFACE_MODE_XGMII;
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else if ((port == FM1_DTSEC1) ||
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(port == FM1_DTSEC2) ||
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(port == FM1_DTSEC3) ||
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(port == FM1_DTSEC4))
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return PHY_INTERFACE_MODE_NONE;
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}
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}
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}
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#endif
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/* Fix me need to handle RGMII here first */
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switch (port) {
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case FM1_DTSEC1:
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case FM1_DTSEC2:
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case FM1_DTSEC3:
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case FM1_DTSEC4:
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case FM1_DTSEC5:
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case FM1_DTSEC6:
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if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
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return PHY_INTERFACE_MODE_SGMII;
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break;
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default:
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return PHY_INTERFACE_MODE_NONE;
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}
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return PHY_INTERFACE_MODE_NONE;
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}
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