415 lines
12 KiB
C
415 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Felix (VSC9959) Ethernet switch driver
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* Copyright 2018-2021 NXP Semiconductors
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*/
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/*
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* This driver is used for the Ethernet switch integrated into NXP LS1028A.
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* Felix switch is derived from Microsemi Ocelot but there are several NXP
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* adaptations that makes the two U-Boot drivers largely incompatible.
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*
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* Felix on LS1028A has 4 front panel ports and two internal ports, connected
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* to ENETC interfaces. We're using one of the ENETC interfaces to push traffic
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* into the switch. Injection/extraction headers are used to identify
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* egress/ingress ports in the switch for Tx/Rx.
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*/
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#include <dm/device_compat.h>
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#include <linux/delay.h>
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#include <net/dsa.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include <pci.h>
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/* defines especially around PCS are reused from enetc */
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#include "../fsl_enetc.h"
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#define PCI_DEVICE_ID_FELIX_ETHSW 0xEEF0
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/* Felix has in fact 6 ports, but we don't use the last internal one */
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#define FELIX_PORT_COUNT 5
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/* Front panel port mask */
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#define FELIX_FP_PORT_MASK 0xf
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/* Register map for BAR4 */
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#define FELIX_SYS 0x010000
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#define FELIX_ES0 0x040000
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#define FELIX_IS1 0x050000
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#define FELIX_IS2 0x060000
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#define FELIX_GMII(port) (0x100000 + (port) * 0x10000)
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#define FELIX_QSYS 0x200000
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#define FELIX_SYS_SYSTEM (FELIX_SYS + 0x00000E00)
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#define FELIX_SYS_SYSTEM_EN BIT(0)
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#define FELIX_SYS_RAM_CTRL (FELIX_SYS + 0x00000F24)
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#define FELIX_SYS_RAM_CTRL_INIT BIT(1)
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#define FELIX_SYS_SYSTEM_PORT_MODE(a) (FELIX_SYS_SYSTEM + 0xC + (a) * 4)
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#define FELIX_SYS_SYSTEM_PORT_MODE_CPU 0x0000001e
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#define FELIX_ES0_TCAM_CTRL (FELIX_ES0 + 0x000003C0)
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#define FELIX_ES0_TCAM_CTRL_EN BIT(0)
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#define FELIX_IS1_TCAM_CTRL (FELIX_IS1 + 0x000003C0)
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#define FELIX_IS1_TCAM_CTRL_EN BIT(0)
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#define FELIX_IS2_TCAM_CTRL (FELIX_IS2 + 0x000003C0)
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#define FELIX_IS2_TCAM_CTRL_EN BIT(0)
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#define FELIX_GMII_CLOCK_CFG(port) (FELIX_GMII(port) + 0x00000000)
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#define FELIX_GMII_CLOCK_CFG_LINK_1G 1
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#define FELIX_GMII_CLOCK_CFG_LINK_100M 2
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#define FELIX_GMII_CLOCK_CFG_LINK_10M 3
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#define FELIX_GMII_MAC_ENA_CFG(port) (FELIX_GMII(port) + 0x0000001C)
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#define FELIX_GMII_MAX_ENA_CFG_TX BIT(0)
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#define FELIX_GMII_MAX_ENA_CFG_RX BIT(4)
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#define FELIX_GMII_MAC_IFG_CFG(port) (FELIX_GMII(port) + 0x0000001C + 0x14)
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#define FELIX_GMII_MAC_IFG_CFG_DEF 0x515
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#define FELIX_QSYS_SYSTEM (FELIX_QSYS + 0x0000F460)
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#define FELIX_QSYS_SYSTEM_SW_PORT_MODE(a) \
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(FELIX_QSYS_SYSTEM + 0x20 + (a) * 4)
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#define FELIX_QSYS_SYSTEM_SW_PORT_ENA BIT(14)
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#define FELIX_QSYS_SYSTEM_SW_PORT_LOSSY BIT(9)
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#define FELIX_QSYS_SYSTEM_SW_PORT_SCH(a) (((a) & 0x3800) << 11)
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#define FELIX_QSYS_SYSTEM_EXT_CPU_CFG (FELIX_QSYS_SYSTEM + 0x80)
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#define FELIX_QSYS_SYSTEM_EXT_CPU_PORT(a) (((a) & 0xf) << 8 | 0xff)
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/* internal MDIO in BAR0 */
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#define FELIX_PM_IMDIO_BASE 0x8030
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/* Serdes block on LS1028A */
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#define FELIX_SERDES_BASE 0x1ea0000L
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#define FELIX_SERDES_LNATECR0(lane) (FELIX_SERDES_BASE + 0x818 + \
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(lane) * 0x40)
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#define FELIX_SERDES_LNATECR0_ADPT_EQ 0x00003000
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#define FELIX_SERDES_SGMIICR1(lane) (FELIX_SERDES_BASE + 0x1804 + \
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(lane) * 0x10)
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#define FELIX_SERDES_SGMIICR1_SGPCS BIT(11)
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#define FELIX_SERDES_SGMIICR1_MDEV(a) (((a) & 0x1f) << 27)
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#define FELIX_PCS_CTRL 0
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#define FELIX_PCS_CTRL_RST BIT(15)
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/*
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* The long prefix format used here contains two dummy MAC addresses, a magic
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* value in place of a VLAN tag followed by the extraction/injection header and
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* the original L2 frame. Out of all this we only use the port ID.
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*/
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#define FELIX_DSA_TAG_LEN sizeof(struct felix_dsa_tag)
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#define FELIX_DSA_TAG_MAGIC 0x0a008088
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#define FELIX_DSA_TAG_INJ_PORT 7
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#define FELIX_DSA_TAG_INJ_PORT_SET(a) (0x1 << ((a) & FELIX_FP_PORT_MASK))
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#define FELIX_DSA_TAG_EXT_PORT 10
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#define FELIX_DSA_TAG_EXT_PORT_GET(a) ((a) >> 3)
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struct felix_dsa_tag {
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uchar d_mac[6];
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uchar s_mac[6];
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u32 magic;
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uchar meta[16];
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};
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struct felix_priv {
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void *regs_base;
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void *imdio_base;
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struct mii_dev imdio;
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};
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/* MDIO wrappers, we're using these to drive internal MDIO to get to serdes */
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static int felix_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
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{
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struct enetc_mdio_priv priv;
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priv.regs_base = bus->priv;
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return enetc_mdio_read_priv(&priv, addr, devad, reg);
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}
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static int felix_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
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u16 val)
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{
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struct enetc_mdio_priv priv;
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priv.regs_base = bus->priv;
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return enetc_mdio_write_priv(&priv, addr, devad, reg, val);
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}
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/* set up serdes for SGMII */
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static void felix_init_sgmii(struct mii_dev *imdio, int pidx, bool an)
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{
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u16 reg;
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/* set up PCS lane address */
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out_le32(FELIX_SERDES_SGMIICR1(pidx), FELIX_SERDES_SGMIICR1_SGPCS |
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FELIX_SERDES_SGMIICR1_MDEV(pidx));
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/*
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* Set to SGMII mode, for 1Gbps enable AN, for 2.5Gbps set fixed speed.
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* Although fixed speed is 1Gbps, we could be running at 2.5Gbps based
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* on PLL configuration. Setting 1G for 2.5G here is counter intuitive
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* but intentional.
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*/
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reg = ENETC_PCS_IF_MODE_SGMII;
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reg |= an ? ENETC_PCS_IF_MODE_SGMII_AN : ENETC_PCS_IF_MODE_SPEED_1G;
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felix_mdio_write(imdio, pidx, MDIO_DEVAD_NONE,
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ENETC_PCS_IF_MODE, reg);
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/* Dev ability - SGMII */
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felix_mdio_write(imdio, pidx, MDIO_DEVAD_NONE,
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ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SGMII);
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/* Adjust link timer for SGMII */
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felix_mdio_write(imdio, pidx, MDIO_DEVAD_NONE,
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ENETC_PCS_LINK_TIMER1, ENETC_PCS_LINK_TIMER1_VAL);
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felix_mdio_write(imdio, pidx, MDIO_DEVAD_NONE,
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ENETC_PCS_LINK_TIMER2, ENETC_PCS_LINK_TIMER2_VAL);
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reg = ENETC_PCS_CR_DEF_VAL;
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reg |= an ? ENETC_PCS_CR_RESET_AN : ENETC_PCS_CR_RST;
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/* restart PCS AN */
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felix_mdio_write(imdio, pidx, MDIO_DEVAD_NONE,
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ENETC_PCS_CR, reg);
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}
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/* set up MAC and serdes for (Q)SXGMII */
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static int felix_init_sxgmii(struct mii_dev *imdio, int pidx)
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{
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int timeout = 1000;
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/* set up transit equalization control on serdes lane */
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out_le32(FELIX_SERDES_LNATECR0(1), FELIX_SERDES_LNATECR0_ADPT_EQ);
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/*reset lane */
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felix_mdio_write(imdio, pidx, MDIO_MMD_PCS, FELIX_PCS_CTRL,
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FELIX_PCS_CTRL_RST);
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while (felix_mdio_read(imdio, pidx, MDIO_MMD_PCS,
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FELIX_PCS_CTRL) & FELIX_PCS_CTRL_RST &&
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--timeout) {
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mdelay(10);
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}
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if (felix_mdio_read(imdio, pidx, MDIO_MMD_PCS,
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FELIX_PCS_CTRL) & FELIX_PCS_CTRL_RST)
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return -ETIME;
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/* Dev ability - SXGMII */
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felix_mdio_write(imdio, pidx, ENETC_PCS_DEVAD_REPL,
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ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII);
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/* Restart PCS AN */
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felix_mdio_write(imdio, pidx, ENETC_PCS_DEVAD_REPL, ENETC_PCS_CR,
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ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN);
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felix_mdio_write(imdio, pidx, ENETC_PCS_DEVAD_REPL,
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ENETC_PCS_REPL_LINK_TIMER_1,
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ENETC_PCS_REPL_LINK_TIMER_1_DEF);
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felix_mdio_write(imdio, pidx, ENETC_PCS_DEVAD_REPL,
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ENETC_PCS_REPL_LINK_TIMER_2,
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ENETC_PCS_REPL_LINK_TIMER_2_DEF);
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return 0;
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}
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/* Apply protocol specific configuration to MAC, serdes as needed */
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static void felix_start_pcs(struct udevice *dev, int port,
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struct phy_device *phy, struct mii_dev *imdio)
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{
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bool autoneg = true;
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if (phy->phy_id == PHY_FIXED_ID ||
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phy->interface == PHY_INTERFACE_MODE_SGMII_2500)
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autoneg = false;
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switch (phy->interface) {
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_SGMII_2500:
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case PHY_INTERFACE_MODE_QSGMII:
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felix_init_sgmii(imdio, port, autoneg);
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break;
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case PHY_INTERFACE_MODE_XGMII:
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case PHY_INTERFACE_MODE_XFI:
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case PHY_INTERFACE_MODE_USXGMII:
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if (felix_init_sxgmii(imdio, port))
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dev_err(dev, "PCS reset timeout on port %d\n", port);
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break;
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default:
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break;
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}
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}
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void felix_init(struct udevice *dev)
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{
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struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
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struct felix_priv *priv = dev_get_priv(dev);
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void *base = priv->regs_base;
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int timeout = 100;
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/* Init core memories */
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out_le32(base + FELIX_SYS_RAM_CTRL, FELIX_SYS_RAM_CTRL_INIT);
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while (in_le32(base + FELIX_SYS_RAM_CTRL) & FELIX_SYS_RAM_CTRL_INIT &&
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--timeout)
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udelay(10);
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if (in_le32(base + FELIX_SYS_RAM_CTRL) & FELIX_SYS_RAM_CTRL_INIT)
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dev_err(dev, "Timeout waiting for switch memories\n");
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/* Start switch core, set up ES0, IS1, IS2 */
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out_le32(base + FELIX_SYS_SYSTEM, FELIX_SYS_SYSTEM_EN);
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out_le32(base + FELIX_ES0_TCAM_CTRL, FELIX_ES0_TCAM_CTRL_EN);
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out_le32(base + FELIX_IS1_TCAM_CTRL, FELIX_IS1_TCAM_CTRL_EN);
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out_le32(base + FELIX_IS2_TCAM_CTRL, FELIX_IS2_TCAM_CTRL_EN);
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udelay(20);
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priv->imdio.read = felix_mdio_read;
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priv->imdio.write = felix_mdio_write;
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priv->imdio.priv = priv->imdio_base + FELIX_PM_IMDIO_BASE;
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strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
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/* set up CPU port */
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out_le32(base + FELIX_QSYS_SYSTEM_EXT_CPU_CFG,
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FELIX_QSYS_SYSTEM_EXT_CPU_PORT(pdata->cpu_port));
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out_le32(base + FELIX_SYS_SYSTEM_PORT_MODE(pdata->cpu_port),
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FELIX_SYS_SYSTEM_PORT_MODE_CPU);
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}
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/*
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* Probe Felix:
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* - enable the PCI function
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* - map BAR 4
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* - init switch core and port registers
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*/
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static int felix_probe(struct udevice *dev)
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{
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struct felix_priv *priv = dev_get_priv(dev);
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if (ofnode_valid(dev_ofnode(dev)) &&
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!ofnode_is_available(dev_ofnode(dev))) {
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dev_dbg(dev, "switch disabled\n");
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return -ENODEV;
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}
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priv->imdio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0);
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if (!priv->imdio_base) {
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dev_err(dev, "failed to map BAR0\n");
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return -EINVAL;
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}
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priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4, 0);
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if (!priv->regs_base) {
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dev_err(dev, "failed to map BAR4\n");
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return -EINVAL;
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}
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/* register internal MDIO for debug */
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if (!miiphy_get_dev_by_name(dev->name)) {
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struct mii_dev *mii_bus;
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mii_bus = mdio_alloc();
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mii_bus->read = felix_mdio_read;
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mii_bus->write = felix_mdio_write;
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mii_bus->priv = priv->imdio_base + FELIX_PM_IMDIO_BASE;
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strncpy(mii_bus->name, dev->name, MDIO_NAME_LEN);
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mdio_register(mii_bus);
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}
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dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
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dsa_set_tagging(dev, FELIX_DSA_TAG_LEN, 0);
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/* set up registers */
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felix_init(dev);
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return 0;
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}
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static int felix_port_enable(struct udevice *dev, int port,
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struct phy_device *phy)
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{
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int supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full;
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struct felix_priv *priv = dev_get_priv(dev);
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void *base = priv->regs_base;
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/* Set up MAC registers */
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out_le32(base + FELIX_GMII_CLOCK_CFG(port),
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FELIX_GMII_CLOCK_CFG_LINK_1G);
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out_le32(base + FELIX_GMII_MAC_IFG_CFG(port),
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FELIX_GMII_MAC_IFG_CFG_DEF);
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out_le32(base + FELIX_GMII_MAC_ENA_CFG(port),
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FELIX_GMII_MAX_ENA_CFG_TX | FELIX_GMII_MAX_ENA_CFG_RX);
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out_le32(base + FELIX_QSYS_SYSTEM_SW_PORT_MODE(port),
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FELIX_QSYS_SYSTEM_SW_PORT_ENA |
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FELIX_QSYS_SYSTEM_SW_PORT_LOSSY |
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FELIX_QSYS_SYSTEM_SW_PORT_SCH(1));
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felix_start_pcs(dev, port, phy, &priv->imdio);
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phy->supported &= supported;
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phy->advertising &= supported;
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phy_config(phy);
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phy_startup(phy);
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return 0;
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}
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static void felix_port_disable(struct udevice *dev, int pidx,
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struct phy_device *phy)
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{
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struct felix_priv *priv = dev_get_priv(dev);
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void *base = priv->regs_base;
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out_le32(base + FELIX_GMII_MAC_ENA_CFG(pidx), 0);
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out_le32(base + FELIX_QSYS_SYSTEM_SW_PORT_MODE(pidx),
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FELIX_QSYS_SYSTEM_SW_PORT_LOSSY |
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FELIX_QSYS_SYSTEM_SW_PORT_SCH(1));
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/*
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* we don't call phy_shutdown here to avoid waiting next time we use
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* the port, but the downside is that remote side will think we're
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* actively processing traffic although we are not.
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*/
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}
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static int felix_xmit(struct udevice *dev, int pidx, void *packet, int length)
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{
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struct felix_dsa_tag *tag = packet;
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tag->magic = FELIX_DSA_TAG_MAGIC;
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tag->meta[FELIX_DSA_TAG_INJ_PORT] = FELIX_DSA_TAG_INJ_PORT_SET(pidx);
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return 0;
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}
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static int felix_rcv(struct udevice *dev, int *pidx, void *packet, int length)
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{
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struct felix_dsa_tag *tag = packet;
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if (tag->magic != FELIX_DSA_TAG_MAGIC)
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return -EINVAL;
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*pidx = FELIX_DSA_TAG_EXT_PORT_GET(tag->meta[FELIX_DSA_TAG_EXT_PORT]);
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return 0;
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}
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static const struct dsa_ops felix_dsa_ops = {
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.port_enable = felix_port_enable,
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.port_disable = felix_port_disable,
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.xmit = felix_xmit,
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.rcv = felix_rcv,
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};
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U_BOOT_DRIVER(felix_ethsw) = {
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.name = "felix-switch",
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.id = UCLASS_DSA,
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.probe = felix_probe,
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.ops = &felix_dsa_ops,
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.priv_auto = sizeof(struct felix_priv),
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};
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static struct pci_device_id felix_ethsw_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_FELIX_ETHSW) },
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{}
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};
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U_BOOT_PCI_DEVICE(felix_ethsw, felix_ethsw_ids);
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