577 lines
15 KiB
C
577 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017 NXP
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*
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* Peng Fan <peng.fan@nxp.com>
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <errno.h>
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#include <dm.h>
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#include <i2c.h>
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#include <log.h>
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#include <power/pmic.h>
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#include <power/regulator.h>
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#include <power/pfuze100_pmic.h>
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/**
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* struct pfuze100_regulator_desc - regulator descriptor
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*
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* @name: Identify name for the regulator.
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* @type: Indicates the regulator type.
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* @uV_step: Voltage increase for each selector.
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* @vsel_reg: Register for adjust regulator voltage for normal.
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* @vsel_mask: Mask bit for setting regulator voltage for normal.
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* @stby_reg: Register for adjust regulator voltage for standby.
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* @stby_mask: Mask bit for setting regulator voltage for standby.
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* @volt_table: Voltage mapping table (if table based mapping).
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* @voltage: Current voltage for REGULATOR_TYPE_FIXED type regulator.
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*/
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struct pfuze100_regulator_desc {
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char *name;
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enum regulator_type type;
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unsigned int uV_step;
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unsigned int vsel_reg;
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unsigned int vsel_mask;
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unsigned int stby_reg;
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unsigned int stby_mask;
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unsigned int *volt_table;
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unsigned int voltage;
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};
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/**
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* struct pfuze100_regulator_plat - platform data for pfuze100
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*
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* @desc: Points the description entry of one regulator of pfuze100
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*/
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struct pfuze100_regulator_plat {
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struct pfuze100_regulator_desc *desc;
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};
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#define PFUZE100_FIXED_REG(_name, base, vol) \
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{ \
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.name = #_name, \
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.type = REGULATOR_TYPE_FIXED, \
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.voltage = (vol), \
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}
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#define PFUZE100_SW_REG(_name, base, step) \
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{ \
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.name = #_name, \
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.type = REGULATOR_TYPE_BUCK, \
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.uV_step = (step), \
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.vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
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.vsel_mask = 0x3F, \
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.stby_reg = (base) + PFUZE100_STBY_OFFSET, \
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.stby_mask = 0x3F, \
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}
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#define PFUZE100_SWB_REG(_name, base, mask, step, voltages) \
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{ \
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.name = #_name, \
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.type = REGULATOR_TYPE_BUCK, \
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.uV_step = (step), \
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.vsel_reg = (base), \
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.vsel_mask = (mask), \
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.volt_table = (voltages), \
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}
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#define PFUZE100_SNVS_REG(_name, base, mask, voltages) \
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{ \
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.name = #_name, \
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.type = REGULATOR_TYPE_OTHER, \
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.vsel_reg = (base), \
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.vsel_mask = (mask), \
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.volt_table = (voltages), \
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}
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#define PFUZE100_VGEN_REG(_name, base, step) \
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{ \
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.name = #_name, \
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.type = REGULATOR_TYPE_LDO, \
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.uV_step = (step), \
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.vsel_reg = (base), \
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.vsel_mask = 0xF, \
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.stby_reg = (base), \
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.stby_mask = 0x20, \
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}
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#define PFUZE3000_VCC_REG(_name, base, step) \
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{ \
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.name = #_name, \
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.type = REGULATOR_TYPE_LDO, \
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.uV_step = (step), \
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.vsel_reg = (base), \
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.vsel_mask = 0x3, \
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.stby_reg = (base), \
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.stby_mask = 0x20, \
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}
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#define PFUZE3000_SW1_REG(_name, base, step) \
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{ \
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.name = #_name, \
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.type = REGULATOR_TYPE_BUCK, \
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.uV_step = (step), \
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.vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
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.vsel_mask = 0x1F, \
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.stby_reg = (base) + PFUZE100_STBY_OFFSET, \
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.stby_mask = 0x1F, \
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}
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#define PFUZE3000_SW2_REG(_name, base, step) \
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{ \
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.name = #_name, \
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.type = REGULATOR_TYPE_BUCK, \
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.uV_step = (step), \
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.vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
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.vsel_mask = 0x7, \
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.stby_reg = (base) + PFUZE100_STBY_OFFSET, \
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.stby_mask = 0x7, \
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}
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#define PFUZE3000_SW3_REG(_name, base, step) \
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{ \
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.name = #_name, \
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.type = REGULATOR_TYPE_BUCK, \
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.uV_step = (step), \
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.vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
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.vsel_mask = 0xF, \
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.stby_reg = (base) + PFUZE100_STBY_OFFSET, \
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.stby_mask = 0xF, \
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}
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static unsigned int pfuze100_swbst[] = {
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5000000, 5050000, 5100000, 5150000
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};
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static unsigned int pfuze100_vsnvs[] = {
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1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000, -1
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};
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static unsigned int pfuze3000_vsnvs[] = {
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-1, -1, -1, -1, -1, -1, 3000000, -1
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};
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static unsigned int pfuze3000_sw2lo[] = {
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1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000
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};
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/* PFUZE100 */
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static struct pfuze100_regulator_desc pfuze100_regulators[] = {
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PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000),
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PFUZE100_SW_REG(sw1c, PFUZE100_SW1CVOL, 25000),
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PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000),
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PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000),
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PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000),
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PFUZE100_SW_REG(sw4, PFUZE100_SW4VOL, 25000),
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PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst),
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PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
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PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000),
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PFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 50000),
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PFUZE100_VGEN_REG(vgen2, PFUZE100_VGEN2VOL, 50000),
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PFUZE100_VGEN_REG(vgen3, PFUZE100_VGEN3VOL, 100000),
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PFUZE100_VGEN_REG(vgen4, PFUZE100_VGEN4VOL, 100000),
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PFUZE100_VGEN_REG(vgen5, PFUZE100_VGEN5VOL, 100000),
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PFUZE100_VGEN_REG(vgen6, PFUZE100_VGEN6VOL, 100000),
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};
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/* PFUZE200 */
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static struct pfuze100_regulator_desc pfuze200_regulators[] = {
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PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000),
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PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000),
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PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000),
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PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000),
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PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst),
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PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
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PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000),
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PFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 50000),
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PFUZE100_VGEN_REG(vgen2, PFUZE100_VGEN2VOL, 50000),
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PFUZE100_VGEN_REG(vgen3, PFUZE100_VGEN3VOL, 100000),
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PFUZE100_VGEN_REG(vgen4, PFUZE100_VGEN4VOL, 100000),
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PFUZE100_VGEN_REG(vgen5, PFUZE100_VGEN5VOL, 100000),
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PFUZE100_VGEN_REG(vgen6, PFUZE100_VGEN6VOL, 100000),
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};
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/* PFUZE3000 */
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static struct pfuze100_regulator_desc pfuze3000_regulators[] = {
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PFUZE3000_SW1_REG(sw1a, PFUZE100_SW1ABVOL, 25000),
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PFUZE3000_SW1_REG(sw1b, PFUZE100_SW1CVOL, 25000),
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PFUZE100_SWB_REG(sw2, PFUZE100_SW2VOL, 0x7, 50000, pfuze3000_sw2lo),
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PFUZE3000_SW3_REG(sw3, PFUZE100_SW3AVOL, 50000),
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PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst),
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PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze3000_vsnvs),
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PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000),
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PFUZE100_VGEN_REG(vldo1, PFUZE100_VGEN1VOL, 100000),
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PFUZE100_VGEN_REG(vldo2, PFUZE100_VGEN2VOL, 50000),
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PFUZE3000_VCC_REG(vccsd, PFUZE100_VGEN3VOL, 150000),
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PFUZE3000_VCC_REG(v33, PFUZE100_VGEN4VOL, 150000),
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PFUZE100_VGEN_REG(vldo3, PFUZE100_VGEN5VOL, 100000),
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PFUZE100_VGEN_REG(vldo4, PFUZE100_VGEN6VOL, 100000),
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};
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#define MODE(_id, _val, _name) { \
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.id = _id, \
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.register_value = _val, \
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.name = _name, \
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}
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/* SWx Buck regulator mode */
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static struct dm_regulator_mode pfuze_sw_modes[] = {
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MODE(OFF_OFF, OFF_OFF, "OFF_OFF"),
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MODE(PWM_OFF, PWM_OFF, "PWM_OFF"),
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MODE(PFM_OFF, PFM_OFF, "PFM_OFF"),
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MODE(APS_OFF, APS_OFF, "APS_OFF"),
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MODE(PWM_PWM, PWM_PWM, "PWM_PWM"),
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MODE(PWM_APS, PWM_APS, "PWM_APS"),
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MODE(APS_APS, APS_APS, "APS_APS"),
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MODE(APS_PFM, APS_PFM, "APS_PFM"),
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MODE(PWM_PFM, PWM_PFM, "PWM_PFM"),
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};
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/* Boost Buck regulator mode for normal operation */
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static struct dm_regulator_mode pfuze_swbst_modes[] = {
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MODE(SWBST_MODE_OFF, SWBST_MODE_OFF , "SWBST_MODE_OFF"),
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MODE(SWBST_MODE_PFM, SWBST_MODE_PFM, "SWBST_MODE_PFM"),
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MODE(SWBST_MODE_AUTO, SWBST_MODE_AUTO, "SWBST_MODE_AUTO"),
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MODE(SWBST_MODE_APS, SWBST_MODE_APS, "SWBST_MODE_APS"),
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};
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/* VGENx LDO regulator mode for normal operation */
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static struct dm_regulator_mode pfuze_ldo_modes[] = {
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MODE(LDO_MODE_OFF, LDO_MODE_OFF, "LDO_MODE_OFF"),
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MODE(LDO_MODE_ON, LDO_MODE_ON, "LDO_MODE_ON"),
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};
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static struct pfuze100_regulator_desc *se_desc(struct pfuze100_regulator_desc *desc,
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int size,
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const char *name)
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{
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int i;
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for (i = 0; i < size; desc++) {
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if (!strcmp(desc->name, name))
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return desc;
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continue;
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}
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return NULL;
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}
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static int pfuze100_regulator_probe(struct udevice *dev)
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{
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struct dm_regulator_uclass_plat *uc_pdata;
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struct pfuze100_regulator_plat *plat = dev_get_plat(dev);
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struct pfuze100_regulator_desc *desc;
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switch (dev_get_driver_data(dev_get_parent(dev))) {
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case PFUZE100:
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desc = se_desc(pfuze100_regulators,
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ARRAY_SIZE(pfuze100_regulators),
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dev->name);
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break;
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case PFUZE200:
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desc = se_desc(pfuze200_regulators,
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ARRAY_SIZE(pfuze200_regulators),
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dev->name);
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break;
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case PFUZE3000:
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desc = se_desc(pfuze3000_regulators,
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ARRAY_SIZE(pfuze3000_regulators),
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dev->name);
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break;
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default:
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debug("Unsupported PFUZE\n");
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return -EINVAL;
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}
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if (!desc) {
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debug("Do not support regulator %s\n", dev->name);
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return -EINVAL;
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}
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plat->desc = desc;
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uc_pdata = dev_get_uclass_plat(dev);
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uc_pdata->type = desc->type;
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if (uc_pdata->type == REGULATOR_TYPE_BUCK) {
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if (!strcmp(dev->name, "swbst")) {
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uc_pdata->mode = pfuze_swbst_modes;
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uc_pdata->mode_count = ARRAY_SIZE(pfuze_swbst_modes);
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} else {
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uc_pdata->mode = pfuze_sw_modes;
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uc_pdata->mode_count = ARRAY_SIZE(pfuze_sw_modes);
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}
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} else if (uc_pdata->type == REGULATOR_TYPE_LDO) {
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uc_pdata->mode = pfuze_ldo_modes;
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uc_pdata->mode_count = ARRAY_SIZE(pfuze_ldo_modes);
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} else {
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uc_pdata->mode = NULL;
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uc_pdata->mode_count = 0;
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}
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return 0;
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}
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static int pfuze100_regulator_mode(struct udevice *dev, int op, int *opmode)
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{
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int val;
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struct pfuze100_regulator_plat *plat = dev_get_plat(dev);
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struct pfuze100_regulator_desc *desc = plat->desc;
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if (op == PMIC_OP_GET) {
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if (desc->type == REGULATOR_TYPE_BUCK) {
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if (!strcmp(dev->name, "swbst")) {
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val = pmic_reg_read(dev->parent,
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desc->vsel_reg);
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if (val < 0)
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return val;
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val &= SWBST_MODE_MASK;
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val >>= SWBST_MODE_SHIFT;
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*opmode = val;
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return 0;
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}
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val = pmic_reg_read(dev->parent,
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desc->vsel_reg +
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PFUZE100_MODE_OFFSET);
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if (val < 0)
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return val;
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val &= SW_MODE_MASK;
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val >>= SW_MODE_SHIFT;
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*opmode = val;
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return 0;
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} else if (desc->type == REGULATOR_TYPE_LDO) {
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val = pmic_reg_read(dev->parent, desc->vsel_reg);
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if (val < 0)
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return val;
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val &= LDO_MODE_MASK;
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val >>= LDO_MODE_SHIFT;
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*opmode = val;
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return 0;
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} else {
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return -EINVAL;
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}
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}
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if (desc->type == REGULATOR_TYPE_BUCK) {
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if (!strcmp(dev->name, "swbst"))
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return pmic_clrsetbits(dev->parent, desc->vsel_reg,
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SWBST_MODE_MASK,
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*opmode << SWBST_MODE_SHIFT);
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val = pmic_clrsetbits(dev->parent,
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desc->vsel_reg + PFUZE100_MODE_OFFSET,
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SW_MODE_MASK,
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*opmode << SW_MODE_SHIFT);
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} else if (desc->type == REGULATOR_TYPE_LDO) {
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val = pmic_clrsetbits(dev->parent, desc->vsel_reg,
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LDO_MODE_MASK,
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*opmode << LDO_MODE_SHIFT);
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return val;
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} else {
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return -EINVAL;
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}
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return 0;
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}
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static int pfuze100_regulator_enable(struct udevice *dev, int op, bool *enable)
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{
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int val;
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int ret, on_off;
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struct dm_regulator_uclass_plat *uc_pdata =
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dev_get_uclass_plat(dev);
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if (op == PMIC_OP_GET) {
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if (!strcmp(dev->name, "vrefddr")) {
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val = pmic_reg_read(dev->parent, PFUZE100_VREFDDRCON);
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if (val < 0)
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return val;
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if (val & VREFDDRCON_EN)
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*enable = true;
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else
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*enable = false;
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return 0;
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}
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ret = pfuze100_regulator_mode(dev, op, &on_off);
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if (ret)
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return ret;
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switch (on_off) {
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/* OFF_OFF, SWBST_MODE_OFF, LDO_MODE_OFF have same value */
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case OFF_OFF:
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*enable = false;
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break;
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default:
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*enable = true;
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break;
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}
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} else if (op == PMIC_OP_SET) {
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if (!strcmp(dev->name, "vrefddr")) {
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val = pmic_reg_read(dev->parent, PFUZE100_VREFDDRCON);
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if (val < 0)
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return val;
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if (val & VREFDDRCON_EN)
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return 0;
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val |= VREFDDRCON_EN;
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return pmic_reg_write(dev->parent, PFUZE100_VREFDDRCON,
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val);
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}
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if (uc_pdata->type == REGULATOR_TYPE_LDO) {
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on_off = *enable ? LDO_MODE_ON : LDO_MODE_OFF;
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} else if (uc_pdata->type == REGULATOR_TYPE_BUCK) {
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if (!strcmp(dev->name, "swbst"))
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on_off = *enable ? SWBST_MODE_AUTO :
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SWBST_MODE_OFF;
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else
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on_off = *enable ? APS_PFM : OFF_OFF;
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} else {
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return -EINVAL;
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}
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return pfuze100_regulator_mode(dev, op, &on_off);
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}
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return 0;
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}
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static int pfuze100_regulator_val(struct udevice *dev, int op, int *uV)
|
|
{
|
|
int i;
|
|
int val;
|
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struct pfuze100_regulator_plat *plat = dev_get_plat(dev);
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|
struct pfuze100_regulator_desc *desc = plat->desc;
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|
struct dm_regulator_uclass_plat *uc_pdata =
|
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dev_get_uclass_plat(dev);
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|
|
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if (op == PMIC_OP_GET) {
|
|
*uV = 0;
|
|
if (uc_pdata->type == REGULATOR_TYPE_FIXED) {
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|
*uV = desc->voltage;
|
|
} else if (desc->volt_table) {
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|
val = pmic_reg_read(dev->parent, desc->vsel_reg);
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|
if (val < 0)
|
|
return val;
|
|
val &= desc->vsel_mask;
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|
*uV = desc->volt_table[val];
|
|
} else {
|
|
if (uc_pdata->min_uV < 0) {
|
|
debug("Need to provide min_uV in dts.\n");
|
|
return -EINVAL;
|
|
}
|
|
val = pmic_reg_read(dev->parent, desc->vsel_reg);
|
|
if (val < 0)
|
|
return val;
|
|
val &= desc->vsel_mask;
|
|
*uV = uc_pdata->min_uV + (int)val * desc->uV_step;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
if (uc_pdata->type == REGULATOR_TYPE_FIXED) {
|
|
debug("Set voltage for REGULATOR_TYPE_FIXED regulator\n");
|
|
return -EINVAL;
|
|
} else if (desc->volt_table) {
|
|
for (i = 0; i <= desc->vsel_mask; i++) {
|
|
if (*uV == desc->volt_table[i])
|
|
break;
|
|
}
|
|
if (i == desc->vsel_mask + 1) {
|
|
debug("Unsupported voltage %u\n", *uV);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return pmic_clrsetbits(dev->parent, desc->vsel_reg,
|
|
desc->vsel_mask, i);
|
|
} else {
|
|
if (uc_pdata->min_uV < 0) {
|
|
debug("Need to provide min_uV in dts.\n");
|
|
return -EINVAL;
|
|
}
|
|
return pmic_clrsetbits(dev->parent, desc->vsel_reg,
|
|
desc->vsel_mask,
|
|
(*uV - uc_pdata->min_uV) / desc->uV_step);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pfuze100_regulator_get_value(struct udevice *dev)
|
|
{
|
|
int uV;
|
|
int ret;
|
|
|
|
ret = pfuze100_regulator_val(dev, PMIC_OP_GET, &uV);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return uV;
|
|
}
|
|
|
|
static int pfuze100_regulator_set_value(struct udevice *dev, int uV)
|
|
{
|
|
return pfuze100_regulator_val(dev, PMIC_OP_SET, &uV);
|
|
}
|
|
|
|
static int pfuze100_regulator_get_enable(struct udevice *dev)
|
|
{
|
|
int ret;
|
|
bool enable = false;
|
|
|
|
ret = pfuze100_regulator_enable(dev, PMIC_OP_GET, &enable);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return enable;
|
|
}
|
|
|
|
static int pfuze100_regulator_set_enable(struct udevice *dev, bool enable)
|
|
{
|
|
return pfuze100_regulator_enable(dev, PMIC_OP_SET, &enable);
|
|
}
|
|
|
|
static int pfuze100_regulator_get_mode(struct udevice *dev)
|
|
{
|
|
int mode;
|
|
int ret;
|
|
|
|
ret = pfuze100_regulator_mode(dev, PMIC_OP_GET, &mode);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return mode;
|
|
}
|
|
|
|
static int pfuze100_regulator_set_mode(struct udevice *dev, int mode)
|
|
{
|
|
return pfuze100_regulator_mode(dev, PMIC_OP_SET, &mode);
|
|
}
|
|
|
|
static const struct dm_regulator_ops pfuze100_regulator_ops = {
|
|
.get_value = pfuze100_regulator_get_value,
|
|
.set_value = pfuze100_regulator_set_value,
|
|
.get_enable = pfuze100_regulator_get_enable,
|
|
.set_enable = pfuze100_regulator_set_enable,
|
|
.get_mode = pfuze100_regulator_get_mode,
|
|
.set_mode = pfuze100_regulator_set_mode,
|
|
};
|
|
|
|
U_BOOT_DRIVER(pfuze100_regulator) = {
|
|
.name = "pfuze100_regulator",
|
|
.id = UCLASS_REGULATOR,
|
|
.ops = &pfuze100_regulator_ops,
|
|
.probe = pfuze100_regulator_probe,
|
|
.plat_auto = sizeof(struct pfuze100_regulator_plat),
|
|
};
|