426 lines
9.9 KiB
C
426 lines
9.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Amlogic GXL DWC3 Glue layer
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*
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* Copyright (C) 2019 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#define DEBUG
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#include <common.h>
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#include <asm-generic/io.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dwc3-uboot.h>
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#include <generic-phy.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <malloc.h>
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#include <regmap.h>
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#include <usb.h>
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#include "core.h"
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#include "gadget.h"
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#include <reset.h>
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#include <clk.h>
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#include <power/regulator.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/compat.h>
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#include <asm/arch/usb-gx.h>
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/* USB Glue Control Registers */
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#define USB_R0 0x00
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#define USB_R0_P30_FSEL_MASK GENMASK(5, 0)
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#define USB_R0_P30_PHY_RESET BIT(6)
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#define USB_R0_P30_TEST_POWERDOWN_HSP BIT(7)
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#define USB_R0_P30_TEST_POWERDOWN_SSP BIT(8)
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#define USB_R0_P30_ACJT_LEVEL_MASK GENMASK(13, 9)
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#define USB_R0_P30_TX_BOOST_LEVEL_MASK GENMASK(16, 14)
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#define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17)
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#define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18)
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#define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19)
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#define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29)
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#define USB_R0_U2D_ACT BIT(31)
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#define USB_R1 0x04
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#define USB_R1_U3H_BIGENDIAN_GS BIT(0)
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#define USB_R1_U3H_PME_ENABLE BIT(1)
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#define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(6, 2)
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#define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(11, 7)
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#define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(15, 12)
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#define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16)
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#define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17)
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#define USB_R1_U3H_HOST_MSI_ENABLE BIT(18)
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#define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19)
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#define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25)
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#define USB_R2 0x08
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#define USB_R2_P30_CR_DATA_IN_MASK GENMASK(15, 0)
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#define USB_R2_P30_CR_READ BIT(16)
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#define USB_R2_P30_CR_WRITE BIT(17)
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#define USB_R2_P30_CR_CAP_ADDR BIT(18)
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#define USB_R2_P30_CR_CAP_DATA BIT(19)
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#define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20)
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#define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26)
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#define USB_R3 0x0c
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#define USB_R3_P30_SSC_ENABLE BIT(0)
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#define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1)
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#define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4)
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#define USB_R3_P30_REF_SSP_EN BIT(13)
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#define USB_R3_P30_LOS_BIAS_MASK GENMASK(18, 16)
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#define USB_R3_P30_LOS_LEVEL_MASK GENMASK(23, 19)
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#define USB_R3_P30_MPLL_MULTIPLIER_MASK GENMASK(30, 24)
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#define USB_R4 0x10
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#define USB_R4_P21_PORT_RESET_0 BIT(0)
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#define USB_R4_P21_SLEEP_M0 BIT(1)
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#define USB_R4_MEM_PD_MASK GENMASK(3, 2)
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#define USB_R4_P21_ONLY BIT(4)
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#define USB_R5 0x14
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#define USB_R5_ID_DIG_SYNC BIT(0)
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#define USB_R5_ID_DIG_REG BIT(1)
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#define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2)
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#define USB_R5_ID_DIG_EN_0 BIT(4)
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#define USB_R5_ID_DIG_EN_1 BIT(5)
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#define USB_R5_ID_DIG_CURR BIT(6)
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#define USB_R5_ID_DIG_IRQ BIT(7)
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#define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8)
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#define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16)
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/* read-only register */
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#define USB_R6 0x18
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#define USB_R6_P30_CR_DATA_OUT_MASK GENMASK(15, 0)
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#define USB_R6_P30_CR_ACK BIT(16)
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enum {
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USB2_HOST_PHY0 = 0,
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USB2_OTG_PHY1,
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USB2_HOST_PHY2,
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PHY_COUNT,
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};
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static const char *phy_names[PHY_COUNT] = {
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"usb2-phy0", "usb2-phy1", "usb2-phy2",
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};
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struct dwc3_meson_gxl {
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struct udevice *dev;
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struct regmap *regmap;
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struct clk clk;
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struct reset_ctl reset;
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struct phy phys[PHY_COUNT];
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enum usb_dr_mode otg_mode;
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enum usb_dr_mode otg_phy_mode;
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unsigned int usb2_ports;
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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struct udevice *vbus_supply;
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#endif
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};
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#define U2P_REG_SIZE 0x20
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#define USB_REG_OFFSET 0x80
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#define USB2_OTG_PHY USB2_OTG_PHY1
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static void dwc3_meson_gxl_usb2_set_mode(struct dwc3_meson_gxl *priv, enum usb_dr_mode mode)
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{
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switch (mode) {
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case USB_DR_MODE_HOST:
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case USB_DR_MODE_OTG:
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case USB_DR_MODE_UNKNOWN:
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regmap_update_bits(priv->regmap, USB_R1,
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USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK, 0);
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regmap_update_bits(priv->regmap, USB_R0,
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USB_R0_U2D_ACT, 0);
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regmap_update_bits(priv->regmap, USB_R4,
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USB_R4_P21_SLEEP_M0, 0);
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break;
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case USB_DR_MODE_PERIPHERAL:
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regmap_update_bits(priv->regmap, USB_R0,
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USB_R0_U2D_ACT, USB_R0_U2D_ACT);
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regmap_update_bits(priv->regmap, USB_R0,
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USB_R0_U2D_SS_SCALEDOWN_MODE_MASK, 0);
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regmap_update_bits(priv->regmap, USB_R4,
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USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0);
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break;
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}
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}
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static int dwc3_meson_gxl_usb2_init(struct dwc3_meson_gxl *priv)
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{
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int i;
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for (i = 0; i < PHY_COUNT; ++i) {
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if (!priv->phys[i].dev)
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continue;
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phy_meson_gxl_usb2_set_mode(&priv->phys[i],
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(i == USB2_OTG_PHY) ? USB_DR_MODE_PERIPHERAL
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: USB_DR_MODE_HOST);
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}
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return 0;
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}
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static int dwc3_meson_gxl_usb_init(struct dwc3_meson_gxl *priv)
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{
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int ret;
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ret = dwc3_meson_gxl_usb2_init(priv);
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if (ret)
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return ret;
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regmap_update_bits(priv->regmap, USB_R1,
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USB_R1_U3H_FLADJ_30MHZ_REG_MASK,
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FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20));
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regmap_update_bits(priv->regmap, USB_R5,
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USB_R5_ID_DIG_EN_0,
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USB_R5_ID_DIG_EN_0);
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regmap_update_bits(priv->regmap, USB_R5,
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USB_R5_ID_DIG_EN_1,
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USB_R5_ID_DIG_EN_1);
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regmap_update_bits(priv->regmap, USB_R5,
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USB_R5_ID_DIG_TH_MASK,
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FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff));
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dwc3_meson_gxl_usb2_set_mode(priv, priv->otg_phy_mode);
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return 0;
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}
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int dwc3_meson_gxl_force_mode(struct udevice *dev, enum usb_dr_mode mode)
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{
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struct dwc3_meson_gxl *priv = dev_get_plat(dev);
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if (!priv)
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return -EINVAL;
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if (mode != USB_DR_MODE_HOST && mode != USB_DR_MODE_PERIPHERAL)
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return -EINVAL;
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if (!priv->phys[USB2_OTG_PHY].dev)
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return -EINVAL;
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if (mode == priv->otg_phy_mode)
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return 0;
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if (mode == USB_DR_MODE_HOST)
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debug("%s: switching to Host Mode\n", __func__);
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else
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debug("%s: switching to Device Mode\n", __func__);
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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if (priv->vbus_supply) {
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int ret = regulator_set_enable(priv->vbus_supply,
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(mode == USB_DR_MODE_PERIPHERAL));
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if (ret)
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return ret;
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}
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#endif
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priv->otg_phy_mode = mode;
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phy_meson_gxl_usb2_set_mode(&priv->phys[USB2_OTG_PHY], mode);
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dwc3_meson_gxl_usb2_set_mode(priv, mode);
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return 0;
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}
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static int dwc3_meson_gxl_get_phys(struct dwc3_meson_gxl *priv)
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{
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int i, ret;
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for (i = 0 ; i < PHY_COUNT ; ++i) {
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ret = generic_phy_get_by_name(priv->dev, phy_names[i],
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&priv->phys[i]);
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if (ret == -ENOENT || ret == -ENODATA) {
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priv->phys[i].dev = NULL;
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continue;
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}
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if (ret)
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return ret;
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priv->usb2_ports++;
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}
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debug("%s: usb2 ports: %d\n", __func__, priv->usb2_ports);
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return 0;
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}
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static int dwc3_meson_gxl_reset_init(struct dwc3_meson_gxl *priv)
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{
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int ret;
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ret = reset_get_by_index(priv->dev, 0, &priv->reset);
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if (ret)
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return ret;
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ret = reset_assert(&priv->reset);
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udelay(1);
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ret |= reset_deassert(&priv->reset);
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if (ret) {
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reset_free(&priv->reset);
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return ret;
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}
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return 0;
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}
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static int dwc3_meson_gxl_clk_init(struct dwc3_meson_gxl *priv)
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{
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int ret;
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ret = clk_get_by_index(priv->dev, 0, &priv->clk);
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if (ret)
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return ret;
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#if CONFIG_IS_ENABLED(CLK)
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ret = clk_enable(&priv->clk);
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if (ret) {
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clk_free(&priv->clk);
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return ret;
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}
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#endif
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return 0;
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}
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static int dwc3_meson_gxl_probe(struct udevice *dev)
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{
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struct dwc3_meson_gxl *priv = dev_get_plat(dev);
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int ret, i;
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priv->dev = dev;
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ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
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if (ret)
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return ret;
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ret = dwc3_meson_gxl_clk_init(priv);
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if (ret)
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return ret;
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ret = dwc3_meson_gxl_reset_init(priv);
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if (ret)
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return ret;
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ret = dwc3_meson_gxl_get_phys(priv);
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if (ret)
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return ret;
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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ret = device_get_supply_regulator(dev, "vbus-supply",
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&priv->vbus_supply);
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if (ret && ret != -ENOENT) {
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pr_err("Failed to get PHY regulator\n");
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return ret;
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}
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if (priv->vbus_supply) {
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ret = regulator_set_enable(priv->vbus_supply, true);
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if (ret)
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return ret;
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}
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#endif
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/* On GXL PHY must be started in device mode for DWC2 init */
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priv->otg_mode = USB_DR_MODE_PERIPHERAL;
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ret = dwc3_meson_gxl_usb_init(priv);
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if (ret)
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return ret;
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priv->otg_mode = usb_get_dr_mode(dev_ofnode(dev));
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if (priv->otg_mode == USB_DR_MODE_PERIPHERAL)
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priv->otg_phy_mode = USB_DR_MODE_PERIPHERAL;
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else
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priv->otg_phy_mode = USB_DR_MODE_HOST;
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for (i = 0 ; i < PHY_COUNT ; ++i) {
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if (!priv->phys[i].dev)
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continue;
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ret = generic_phy_init(&priv->phys[i]);
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if (ret)
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goto err_phy_init;
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}
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for (i = 0; i < PHY_COUNT; ++i) {
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if (!priv->phys[i].dev)
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continue;
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ret = generic_phy_power_on(&priv->phys[i]);
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if (ret)
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goto err_phy_init;
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}
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if (priv->phys[USB2_OTG_PHY].dev)
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phy_meson_gxl_usb2_set_mode(&priv->phys[USB2_OTG_PHY],
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priv->otg_phy_mode);
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dwc3_meson_gxl_usb2_set_mode(priv, priv->otg_phy_mode);
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return 0;
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err_phy_init:
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for (i = 0 ; i < PHY_COUNT ; ++i) {
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if (!priv->phys[i].dev)
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continue;
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generic_phy_exit(&priv->phys[i]);
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}
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return ret;
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}
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static int dwc3_meson_gxl_remove(struct udevice *dev)
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{
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struct dwc3_meson_gxl *priv = dev_get_plat(dev);
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int i;
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reset_release_all(&priv->reset, 1);
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clk_release_all(&priv->clk, 1);
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for (i = 0; i < PHY_COUNT; ++i) {
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if (!priv->phys[i].dev)
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continue;
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generic_phy_power_off(&priv->phys[i]);
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}
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for (i = 0 ; i < PHY_COUNT ; ++i) {
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if (!priv->phys[i].dev)
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continue;
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generic_phy_exit(&priv->phys[i]);
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}
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return dm_scan_fdt_dev(dev);
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}
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static const struct udevice_id dwc3_meson_gxl_ids[] = {
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{ .compatible = "amlogic,meson-gxl-usb-ctrl" },
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{ .compatible = "amlogic,meson-gxm-usb-ctrl" },
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{ }
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};
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U_BOOT_DRIVER(dwc3_generic_wrapper) = {
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.name = "dwc3-meson-gxl",
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.id = UCLASS_SIMPLE_BUS,
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.of_match = dwc3_meson_gxl_ids,
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.probe = dwc3_meson_gxl_probe,
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.remove = dwc3_meson_gxl_remove,
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.plat_auto = sizeof(struct dwc3_meson_gxl),
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};
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