161 lines
4.2 KiB
C
161 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2017-2018 NXP
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* Copyright 2019 Siemens AG
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*/
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#ifndef __IMX8X_CAPRICORN_H
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#define __IMX8X_CAPRICORN_H
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#include <linux/sizes.h>
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#include <asm/arch/imx-regs.h>
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#include "siemens-env-common.h"
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#include "siemens-ccp-common.h"
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/* SPL config */
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_MAX_SIZE (124 * 1024)
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#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
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#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
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#define CONFIG_SPL_STACK 0x013E000
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#define CONFIG_SPL_BSS_START_ADDR 0x00128000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
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#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
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#define CONFIG_MALLOC_F_ADDR 0x00120000
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#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
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#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
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#endif /* CONFIG_SPL_BUILD */
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#define CONFIG_FACTORYSET
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#undef CONFIG_IDENT_STRING
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#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "07")
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#define CONFIG_REMAKE_ELF
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/* ENET Config */
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#define CONFIG_FEC_XCV_TYPE RMII
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/* ENET1 connects to base board and MUX with ESAI */
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#define CONFIG_FEC_ENET_DEV 1
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#define CONFIG_FEC_MXC_PHYADDR 0x0
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#define CONFIG_ETHPRIME "eth1"
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/* I2C Configuration */
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_SYS_I2C_SPEED 400000
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/* EEPROM */
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#define EEPROM_I2C_BUS 0 /* I2C0 */
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#define EEPROM_I2C_ADDR 0x50
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/* PCA9552 */
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#define PCA9552_1_I2C_BUS 1 /* I2C1 */
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#define PCA9552_1_I2C_ADDR 0x60
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#endif /* !CONFIG_SPL_BUILD */
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/* AHAB */
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#ifdef CONFIG_AHAB_BOOT
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#define AHAB_ENV "sec_boot=yes\0"
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#else
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#define AHAB_ENV "sec_boot=no\0"
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#endif
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#define MFG_ENV_SETTINGS_DEFAULT \
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"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
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"rdinit=/linuxrc " \
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"clk_ignore_unused "\
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"\0" \
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"kboot=booti\0"\
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"bootcmd_mfg=run mfgtool_args;" \
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"if iminfo ${initrd_addr}; then " \
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"if test ${tee} = yes; then " \
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"bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \
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"else " \
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"booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \
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"fi; " \
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"else " \
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"echo \"Run fastboot ...\"; fastboot 0; " \
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"fi;\0"
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/* Boot M4 */
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#define M4_BOOT_ENV \
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"m4_0_image=m4_0.bin\0" \
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"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \
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"${loadaddr} ${m4_0_image}\0" \
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"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
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#define CONFIG_MFG_ENV_SETTINGS \
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MFG_ENV_SETTINGS_DEFAULT \
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"initrd_addr=0x83100000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"emmc_dev=0\0"
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_MFG_ENV_SETTINGS \
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M4_BOOT_ENV \
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AHAB_ENV \
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ENV_COMMON \
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"script=boot.scr\0" \
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"image=Image\0" \
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"panel=NULL\0" \
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"console=ttyLP2\0" \
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"fdt_addr=0x83000000\0" \
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"fdt_high=0xffffffffffffffff\0" \
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"cntr_addr=0x88000000\0" \
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"cntr_file=os_cntr_signed.bin\0" \
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"initrd_addr=0x83800000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"netdev=eth0\0" \
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"nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \
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"hostname=capricorn\0" \
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ENV_EMMC \
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ENV_NET
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#define CONFIG_BOOTCOMMAND \
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"if usrbutton; then " \
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"run flash_self_test; " \
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"reset; " \
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"fi;" \
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"run flash_self;" \
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"reset;"
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/* Default location for tftp and bootm */
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#define CONFIG_LOADADDR 0x80280000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
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/* On CCP board, USDHC1 is for eMMC */
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#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* eMMC */
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#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define PHYS_SDRAM_1 0x80000000
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#define PHYS_SDRAM_2 0x880000000
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/* DDR3 board total DDR is 1 GB */
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#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
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#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
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/* Console buffer and boot args */
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#define CONFIG_SYS_CBSIZE 2048
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#define CONFIG_SYS_MAXARGS 64
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY 8000000 /* 8MHz */
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#define BOOTAUX_RESERVED_MEM_BASE 0x88000000
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#define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */
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#endif /* __IMX8X_CAPRICORN_H */
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