298 lines
7.9 KiB
C
298 lines
7.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2013
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* Based on:
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* Copyright (c) 2011 IDS GmbH, Germany
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* Sergej Stepanov <ste@ids.de>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <linux/stringify.h>
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_BOOT_RETRY_TIME 900
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#define CONFIG_BOOT_RETRY_MIN 30
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#define CONFIG_RESET_TO_RETRY
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#define CONFIG_SYS_SICRH 0x00000000
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#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
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#define CONFIG_HWCONFIG
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/*
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* Definitions for initial stack pointer and data area (in DCACHE )
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*/
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_SIZE 0x100
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
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- CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*
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* Internal Definitions
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*/
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/*
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* DDR Setup
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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/*
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* Manually set up DDR parameters,
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* as this board has not the SPD connected to I2C.
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*/
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#define CONFIG_SYS_DDR_SIZE 256 /* MB */
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#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\
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0x00010000 |\
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CSCONFIG_ROW_BIT_13 |\
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CSCONFIG_COL_BIT_10)
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#define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \
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CSCONFIG_BANK_BIT_3)
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#define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */
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#define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
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(3 << TIMING_CFG0_WRT_SHIFT) |\
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(3 << TIMING_CFG0_RRT_SHIFT) |\
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(3 << TIMING_CFG0_WWT_SHIFT) |\
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(6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
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(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
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(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
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(2 << TIMING_CFG0_MRS_CYC_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
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(12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
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(4 << TIMING_CFG1_ACTTORW_SHIFT) |\
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(7 << TIMING_CFG1_CASLAT_SHIFT) |\
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(4 << TIMING_CFG1_REFREC_SHIFT) |\
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(4 << TIMING_CFG1_WRREC_SHIFT) |\
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(2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
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(2 << TIMING_CFG1_WRTORD_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
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(5 << TIMING_CFG2_CPO_SHIFT) |\
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(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
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(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
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(0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
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(1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
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(6 << TIMING_CFG2_FOUR_ACT_SHIFT))
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#define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
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(0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
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#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\
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SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
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SDRAM_CFG_DBW_32 |\
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SDRAM_CFG_SDRAM_TYPE_DDR2)
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#define CONFIG_SYS_SDRAM_CFG2 0x00401000
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#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
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(0x0242 << SDRAM_MODE_SD_SHIFT))
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#define CONFIG_SYS_DDR_MODE_2 0x00000000
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#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
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#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
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DDRCDR_PZ_NOMZ |\
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DDRCDR_NZ_NOMZ |\
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DDRCDR_ODT |\
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DDRCDR_M_ODR |\
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DDRCDR_Q_DRN)
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/*
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* on-board devices
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*/
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#define CONFIG_TSEC1
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#define CONFIG_TSEC2
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/*
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* NOR FLASH setup
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*/
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
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#define CONFIG_FLASH_SHOW_PROGRESS 50
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#define CONFIG_SYS_FLASH_BASE 0xFF800000
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#define CONFIG_SYS_FLASH_SIZE 8
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 128
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500
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/*
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* NAND FLASH setup
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*/
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#define CONFIG_SYS_NAND_BASE 0xE1000000
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_MAX_CHIPS 1
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#define CONFIG_NAND_FSL_ELBC
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#define CONFIG_SYS_NAND_PAGE_SIZE (2048)
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
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#define NAND_CACHE_PAGES 64
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/*
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* MRAM setup
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*/
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#define CONFIG_SYS_MRAM_BASE 0xE2000000
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#define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
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#define CONFIG_SYS_OR_TIMING_MRAM
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/*
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* CPLD setup
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*/
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#define CONFIG_SYS_CPLD_BASE 0xE3000000
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#define CONFIG_SYS_CPLD_SIZE 0x8000
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#define CONFIG_SYS_OR_TIMING_MRAM
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/*
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* HW-Watchdog
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*/
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#define CONFIG_WATCHDOG 1
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#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
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/*
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* I2C setup
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*/
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51
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/*
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* Ethernet setup
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*/
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#ifdef CONFIG_TSEC1
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#define CONFIG_HAS_ETH0
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_SYS_TSEC1_OFFSET 0x24000
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#define TSEC1_PHY_ADDR 0x1
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#define TSEC1_FLAGS TSEC_GIGABIT
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#define TSEC1_PHYIDX 0
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#endif
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#ifdef CONFIG_TSEC2
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#define CONFIG_HAS_ETH1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define CONFIG_SYS_TSEC2_OFFSET 0x25000
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#define TSEC2_PHY_ADDR 0x3
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#define TSEC2_FLAGS TSEC_GIGABIT
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#define TSEC2_PHYIDX 0
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#endif
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#define CONFIG_ETHPRIME "TSEC1"
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/*
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* Serial Port
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
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#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
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#define CONFIG_HAS_FSL_DR_USB
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#define CONFIG_SYS_SCCR_USBDRCM 3
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/*
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* U-Boot environment setup
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* The reserved memory
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024)
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/*
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* Environment Configuration
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*/
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#define CONFIG_NETDEV eth1
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#define CONFIG_HOSTNAME "ids8313"
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#define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
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#define CONFIG_BOOTFILE "ids8313/uImage"
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#define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
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#define CONFIG_FDTFILE "ids8313/ids8313.dtb"
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#define CONFIG_LOADADDR 0x400000
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#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
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/* Initial Memory map for Linux*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_LOAD_ADDR 0x100000
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#define CONFIG_LOADS_ECHO
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#define CONFIG_TIMESTAMP
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#define CONFIG_BOOTCOMMAND "run boot_cramfs"
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE
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#define CONFIG_JFFS2_NAND
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#define CONFIG_JFFS2_DEV "0"
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/* mtdparts command line support */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=" __stringify(CONFIG_NETDEV) "\0" \
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"ethprime=TSEC1\0" \
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"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
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"tftpflash=tftpboot ${loadaddr} ${uboot}; " \
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"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
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" +${filesize}; " \
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"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
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" +${filesize}; " \
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"cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
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" ${filesize}; " \
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"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
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" +${filesize}; " \
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"cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
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" ${filesize}\0" \
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"console=ttyS0\0" \
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"fdtaddr=0x780000\0" \
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"kernel_addr=ff800000\0" \
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"fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
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"setbootargs=setenv bootargs " \
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"root=${rootdev} rw console=${console}," \
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"${baudrate} ${othbootargs}\0" \
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"setipargs=setenv bootargs root=${rootdev} rw " \
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"nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:" \
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"${netmask}:${hostname}:${netdev}:off " \
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"console=${console},${baudrate} ${othbootargs}\0" \
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"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
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"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
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"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
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"\0"
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv rootdev /dev/nfs;" \
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"run setipargs;run addmtd;" \
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"tftp ${loadaddr} ${bootfile};" \
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"tftp ${fdtaddr} ${fdtfile};" \
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"fdt addr ${fdtaddr};" \
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"bootm ${loadaddr} - ${fdtaddr}"
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/* UBI Support */
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#endif /* __CONFIG_H */
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