27 lines
698 B
C
27 lines
698 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2019-2020
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* Marvell <www.marvell.com>
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*/
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#ifndef __OCTEON_COMMON_H__
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#define __OCTEON_COMMON_H__
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#if defined(CONFIG_RAM_OCTEON)
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#define CONFIG_SYS_MALLOC_LEN (16 << 20)
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#define CONFIG_SYS_INIT_SP_OFFSET 0x20100000
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#else
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/* No DDR init -> run in L2 cache with limited resources */
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#define CONFIG_SYS_MALLOC_LEN (256 << 10)
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#define CONFIG_SYS_INIT_SP_OFFSET 0x00180000
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#endif
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#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (1 << 20))
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
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#endif /* __OCTEON_COMMON_H__ */
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