54 lines
1.4 KiB
C
54 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2020 Hitachi ABB Power Grids
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*/
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#ifndef __CONFIG_PG_WCOM_EXPU1_H
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#define __CONFIG_PG_WCOM_EXPU1_H
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#define WCOM_EXPU1
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#define CONFIG_HOSTNAME "EXPU1"
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#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
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#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
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/* CLIPS FPGA Definitions */
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#define CONFIG_SYS_CSPR3_EXT (0x00)
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#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \
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CSPR_PORT_SIZE_8 | \
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CSPR_MSEL_GPCM | \
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CSPR_V)
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#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
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#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \
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CSOR_GPCM_TRHZ_40)
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#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
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FTIM0_GPCM_TEADC(0x7) | \
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FTIM0_GPCM_TEAHC(0x2))
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#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
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FTIM1_GPCM_TRAD(0x12))
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#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
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FTIM2_GPCM_TCH(0x1) | \
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FTIM2_GPCM_TWP(0x12))
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#define CONFIG_SYS_CS3_FTIM3 0x04000000
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/* PRST */
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#define WCOM_CLIPS_RST 0
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#define WCOM_QSFP_RST 1
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#define WCOM_PHY_RST 2
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#define WCOM_TMG_RST 3
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#define KM_DBG_ETH_RST 15
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/* QRIO GPIOs used for deblocking */
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#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A
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#define KM_I2C_DEBLOCK_SCL 20
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#define KM_I2C_DEBLOCK_SDA 21
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/* ZL30343 on SPI */
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#define WCOM_ZL30343_CFG_ADDR 0xe8070000
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#define WCOM_ZL30343_SPI_BUS 0
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#define WCOM_ZL30343_CS 0
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#include "km/pg-wcom-ls102xa.h"
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#endif /* __CONFIG_PG_WCOM_EXPU1_H */
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