60 lines
1.4 KiB
C
60 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*/
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#ifndef __CONFIG_PX30_COMMON_H
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#define __CONFIG_PX30_COMMON_H
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#include "rockchip-common.h"
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_NS16550_MEM32
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#define CONFIG_ROCKCHIP_STIMER_BASE 0xff220020
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#define COUNTER_FREQUENCY 24000000
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/* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */
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#define CONFIG_IRAM_BASE 0xff020000
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#define CONFIG_SYS_INIT_SP_ADDR 0x00400000
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#define CONFIG_SYS_LOAD_ADDR 0x00800800
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#define CONFIG_SPL_STACK 0x00400000
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#define CONFIG_SPL_MAX_SIZE 0x20000
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#define CONFIG_SPL_BSS_START_ADDR 0x4000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x4000
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
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#define GICD_BASE 0xff131000
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#define GICC_BASE 0xff132000
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
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#define CONFIG_SYS_SDRAM_BASE 0
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#define SDRAM_MAX_SIZE 0xff000000
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#define SDRAM_BANK_SIZE (2UL << 30)
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#ifndef CONFIG_SPL_BUILD
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#define ENV_MEM_LAYOUT_SETTINGS \
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"scriptaddr=0x00500000\0" \
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"pxefile_addr_r=0x00600000\0" \
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"fdt_addr_r=0x08300000\0" \
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"kernel_addr_r=0x00280000\0" \
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"kernel_addr_c=0x03e80000\0" \
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"ramdisk_addr_r=0x0a200000\0"
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#include <config_distro_bootcmd.h>
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#define CONFIG_EXTRA_ENV_SETTINGS \
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ENV_MEM_LAYOUT_SETTINGS \
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"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"partitions=" PARTS_DEFAULT \
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ROCKCHIP_DEVICE_SETTINGS \
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BOOTENV
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#endif
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#endif
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