59 lines
1.5 KiB
C
59 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*/
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#ifndef __CONFIG_RK3308_COMMON_H
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#define __CONFIG_RK3308_COMMON_H
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#include "rockchip-common.h"
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
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#define CONFIG_SPL_MAX_SIZE 0x20000
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#define CONFIG_SPL_BSS_START_ADDR 0x00400000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
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#define CONFIG_SYS_NS16550_MEM32
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#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0
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#define CONFIG_IRAM_BASE 0xfff80000
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#define CONFIG_SYS_INIT_SP_ADDR 0x00800000
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#define CONFIG_SYS_LOAD_ADDR 0x00C00800
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#define CONFIG_SPL_STACK 0x00400000
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
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#define COUNTER_FREQUENCY 24000000
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
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#define CONFIG_SYS_SDRAM_BASE 0
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#define SDRAM_MAX_SIZE 0xff000000
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#define SDRAM_BANK_SIZE (2UL << 30)
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#ifndef CONFIG_SPL_BUILD
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#define ENV_MEM_LAYOUT_SETTINGS \
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"scriptaddr=0x00500000\0" \
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"pxefile_addr_r=0x00600000\0" \
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"fdt_addr_r=0x02800000\0" \
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"kernel_addr_r=0x00680000\0" \
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"ramdisk_addr_r=0x04000000\0"
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#include <config_distro_bootcmd.h>
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#define CONFIG_EXTRA_ENV_SETTINGS \
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ENV_MEM_LAYOUT_SETTINGS \
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"partitions=" PARTS_DEFAULT \
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ROCKCHIP_DEVICE_SETTINGS \
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BOOTENV
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#endif
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#endif
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