33 lines
765 B
C
33 lines
765 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2013 - 2017 Xilinx.
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*
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* Configuration settings for the Xilinx Zynq CSE board.
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* See zynq-common.h for Zynq common configs
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*/
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#ifndef __CONFIG_ZYNQ_CSE_H
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#define __CONFIG_ZYNQ_CSE_H
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#include <configs/zynq-common.h>
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/* Undef unneeded configs */
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#undef CONFIG_EXTRA_ENV_SETTINGS
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#undef CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_CBSIZE 1024
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#undef CONFIG_SYS_INIT_RAM_ADDR
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#undef CONFIG_SYS_INIT_RAM_SIZE
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
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#undef CONFIG_SPL_BSS_START_ADDR
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#undef CONFIG_SPL_BSS_MAX_SIZE
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#define CONFIG_SPL_BSS_START_ADDR 0x20000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x8000
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#endif /* __CONFIG_ZYNQ_CSE_H */
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