101 lines
2.0 KiB
C
101 lines
2.0 KiB
C
/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/mrccache.h>
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#include <asm/post.h>
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#include <asm/processor.h>
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#include <asm/fsp/fsp_support.h>
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DECLARE_GLOBAL_DATA_PTR;
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int print_cpuinfo(void)
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{
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post_code(POST_CPU_INFO);
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return default_print_cpuinfo();
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}
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int fsp_init_phase_pci(void)
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{
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u32 status;
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/* call into FspNotify */
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debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
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status = fsp_notify(NULL, INIT_PHASE_PCI);
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if (status)
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debug("fail, error code %x\n", status);
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else
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debug("OK\n");
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return status ? -EPERM : 0;
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}
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void board_final_cleanup(void)
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{
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u32 status;
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/* call into FspNotify */
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debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
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status = fsp_notify(NULL, INIT_PHASE_BOOT);
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if (status)
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debug("fail, error code %x\n", status);
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else
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debug("OK\n");
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return;
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}
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static __maybe_unused void *fsp_prepare_mrc_cache(void)
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{
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struct mrc_data_container *cache;
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struct mrc_region entry;
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int ret;
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ret = mrccache_get_region(NULL, &entry);
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if (ret)
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return NULL;
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cache = mrccache_find_current(&entry);
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if (!cache)
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return NULL;
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debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
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cache->data, cache->data_size, cache->checksum);
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return cache->data;
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}
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int x86_fsp_init(void)
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{
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void *nvs;
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if (!gd->arch.hob_list) {
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#ifdef CONFIG_ENABLE_MRC_CACHE
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nvs = fsp_prepare_mrc_cache();
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#else
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nvs = NULL;
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#endif
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/*
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* The first time we enter here, call fsp_init().
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* Note the execution does not return to this function,
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* instead it jumps to fsp_continue().
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*/
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fsp_init(CONFIG_FSP_TEMP_RAM_ADDR, BOOT_FULL_CONFIG, nvs);
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} else {
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/*
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* The second time we enter here, adjust the size of malloc()
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* pool before relocation. Given gd->malloc_base was adjusted
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* after the call to board_init_f_mem() in arch/x86/cpu/start.S,
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* we should fix up gd->malloc_limit here.
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*/
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gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN;
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}
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return 0;
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}
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