154 lines
4.4 KiB
C
154 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <init.h>
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#include <miiphy.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <linux/mbus.h>
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#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
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#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
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DECLARE_GLOBAL_DATA_PTR;
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/* Base addresses for the external device chip selects */
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#define DEV_CS0_BASE 0xe0000000
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#define DEV_CS1_BASE 0xe1000000
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#define DEV_CS2_BASE 0xe2000000
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#define DEV_CS3_BASE 0xe3000000
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/* DDR3 static configuration */
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MV_DRAM_MC_INIT ddr3_b0_maxbcm[MV_MAX_DDR3_STATIC_SIZE] = {
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{0x00001400, 0x7301CC30}, /* DDR SDRAM Configuration Register */
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{0x00001404, 0x30000820}, /* Dunit Control Low Register */
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{0x00001408, 0x5515BAAB}, /* DDR SDRAM Timing (Low) Register */
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{0x0000140C, 0x38DA3F97}, /* DDR SDRAM Timing (High) Register */
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{0x00001410, 0x20100005}, /* DDR SDRAM Address Control Register */
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{0x00001414, 0x0000F3FF}, /* DDR SDRAM Open Pages Control Reg */
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{0x00001418, 0x00000e00}, /* DDR SDRAM Operation Register */
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{0x0000141C, 0x00000672}, /* DDR SDRAM Mode Register */
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{0x00001420, 0x00000004}, /* DDR SDRAM Extended Mode Register */
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{0x00001424, 0x0000F3FF}, /* Dunit Control High Register */
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{0x00001428, 0x0011A940}, /* Dunit Control High Register */
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{0x0000142C, 0x014C5134}, /* Dunit Control High Register */
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{0x0000147C, 0x0000D771},
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{0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */
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{0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */
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{0x000014A0, 0x00000001},
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{0x000014A8, 0x00000101},
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/* Recommended Settings from Marvell for 4 x 16 bit devices: */
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{0x000014C0, 0x192424C9}, /* DRAM addr and Ctrl Driving Strenght*/
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{0x000014C4, 0xAAA24C9}, /* DRAM Data and DQS Driving Strenght */
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/*
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* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the
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* training sequence
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*/
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{0x000200e8, 0x3FFF0E01},
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{0x00020184, 0x3FFFFFE0}, /* Close fast path Window to - 2G */
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{0x0001504, 0x3FFFFFE1}, /* CS0 Size */
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{0x000150C, 0x00000000}, /* CS1 Size */
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{0x0001514, 0x00000000}, /* CS2 Size */
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{0x000151C, 0x00000000}, /* CS3 Size */
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{0x0020220, 0x00000007}, /* Reserved */
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{0x00001538, 0x0000000B}, /* Read Data Sample Delays Register */
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{0x0000153C, 0x0000000B}, /* Read Data Ready Delay Register */
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{0x000015D0, 0x00000670}, /* MR0 */
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{0x000015D4, 0x00000044}, /* MR1 */
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{0x000015D8, 0x00000018}, /* MR2 */
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{0x000015DC, 0x00000000}, /* MR3 */
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{0x000015E0, 0x00000001},
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{0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */
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{0x000015EC, 0xF800A225}, /* DDR PHY */
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{0x0, 0x0}
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};
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MV_DRAM_MODES maxbcm_ddr_modes[MV_DDR3_MODES_NUMBER] = {
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{"maxbcm_1600-800", 0xB, 0x5, 0x0, A0, ddr3_b0_maxbcm, NULL},
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};
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extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
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/* MAXBCM: SERDES 0-4 PCIE, Serdes 7 = SGMII 0, all others = unconnected */
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MV_BIN_SERDES_CFG maxbcm_serdes_cfg[] = {
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{ MV_PEX_ROOT_COMPLEX, 0x20011111, 0x00000000,
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{ PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_DISABLED,
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PEX_BUS_DISABLED },
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0x1f, serdes_change_m_phy
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}
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};
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MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
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{
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/* Only one mode supported for this board */
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return &maxbcm_ddr_modes[0];
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}
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MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
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{
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return &maxbcm_serdes_cfg[0];
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}
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int board_early_init_f(void)
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{
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/*
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* Don't configure MPP (pin multiplexing) and GPIO here,
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* its already done in bin_hdr
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*/
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/*
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* Setup some board specific mbus address windows
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*/
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mbus_dt_setup_win(DEV_CS0_BASE, 16 << 20,
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CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS0);
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mbus_dt_setup_win(DEV_CS1_BASE, 16 << 20,
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CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
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mbus_dt_setup_win(DEV_CS2_BASE, 16 << 20,
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CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS2);
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mbus_dt_setup_win(DEV_CS3_BASE, 16 << 20,
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CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS3);
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: maxBCM\n");
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return 0;
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}
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/* Configure and enable MV88E6185 switch */
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int board_phy_config(struct phy_device *phydev)
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{
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/*
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* todo:
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* Fill this with the real setup / config code.
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* Please see board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
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* for details.
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*/
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printf("88E6185 Initialized\n");
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return 0;
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}
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