46 lines
1.1 KiB
C
46 lines
1.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef LPDDR4_AM6X_H
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#define LPDDR4_AM6X_H
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#ifdef CONFIG_K3_AM64_DDRSS
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#include "lpddr4_am64_ctl_regs_rw_masks.h"
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#elif CONFIG_K3_AM62A_DDRSS
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#include "lpddr4_am62a_ctl_regs_rw_masks.h"
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#endif
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#ifdef CONFIG_K3_AM64_DDRSS
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#define DSLICE_NUM (2U)
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#define ASLICE_NUM (2U)
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#define DSLICE0_REG_COUNT (126U)
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#define DSLICE1_REG_COUNT (126U)
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#define ASLICE0_REG_COUNT (42U)
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#define ASLICE1_REG_COUNT (42U)
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#define ASLICE2_REG_COUNT (42U)
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#define PHY_CORE_REG_COUNT (126U)
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#elif CONFIG_K3_AM62A_DDRSS
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#define DSLICE_NUM (4U)
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#define ASLICE_NUM (3U)
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#define DSLICE0_REG_COUNT (136U)
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#define DSLICE1_REG_COUNT (136U)
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#define DSLICE2_REG_COUNT (136U)
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#define DSLICE3_REG_COUNT (136U)
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#define ASLICE0_REG_COUNT (48U)
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#define ASLICE1_REG_COUNT (48U)
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#define ASLICE2_REG_COUNT (48U)
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#define PHY_CORE_REG_COUNT (132U)
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#endif
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#define GRP_SHIFT 1
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#define INT_SHIFT 2
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#endif /* LPDDR4_AM6X_H */
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