49 lines
1.5 KiB
C
49 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013 Altera Corporation <www.altera.com>
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*/
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#ifndef _FREEZE_CONTROLLER_H_
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#define _FREEZE_CONTROLLER_H_
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struct socfpga_freeze_controller {
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u32 vioctrl;
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u32 padding[3];
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u32 hioctrl;
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u32 src;
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u32 hwctrl;
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};
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#define FREEZE_CHANNEL_NUM (4)
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typedef enum {
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FREEZE_CTRL_FROZEN = 0,
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FREEZE_CTRL_THAWED = 1
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} FREEZE_CTRL_CHAN_STATE;
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#define SYSMGR_FRZCTRL_ADDRESS 0x40
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#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0
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#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1
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#define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010
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#define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008
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#define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004
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#define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002
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#define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001
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#define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010
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#define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008
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#define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004
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#define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002
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#define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001
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#define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080
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#define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040
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#define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100
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#define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020
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#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
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#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
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#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
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void sys_mgr_frzctrl_freeze_req(void);
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void sys_mgr_frzctrl_thaw_req(void);
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#endif /* _FREEZE_CONTROLLER_H_ */
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