182 lines
3.3 KiB
C
182 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2017 Tuomas Tynkkynen
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <efi.h>
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#include <efi_loader.h>
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#include <fdtdec.h>
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#include <init.h>
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#include <log.h>
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#include <virtio_types.h>
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#include <virtio.h>
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#include <linux/kernel.h>
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#ifdef CONFIG_ARM64
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#include <asm/armv8/mmu.h>
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#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT)
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struct efi_fw_image fw_images[] = {
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#if defined(CONFIG_TARGET_QEMU_ARM_32BIT)
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{
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.image_type_id = QEMU_ARM_UBOOT_IMAGE_GUID,
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.fw_name = u"Qemu-Arm-UBOOT",
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.image_index = 1,
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},
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#elif defined(CONFIG_TARGET_QEMU_ARM_64BIT)
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{
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.image_type_id = QEMU_ARM64_UBOOT_IMAGE_GUID,
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.fw_name = u"Qemu-Arm-UBOOT",
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.image_index = 1,
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},
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#endif
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};
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struct efi_capsule_update_info update_info = {
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.images = fw_images,
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};
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u8 num_image_type_guids = ARRAY_SIZE(fw_images);
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#endif /* EFI_HAVE_CAPSULE_SUPPORT */
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static struct mm_region qemu_arm64_mem_map[] = {
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{
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/* Flash */
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.virt = 0x00000000UL,
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.phys = 0x00000000UL,
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.size = 0x08000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* Lowmem peripherals */
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.virt = 0x08000000UL,
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.phys = 0x08000000UL,
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.size = 0x38000000,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* RAM */
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 255UL * SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* Highmem PCI-E ECAM memory area */
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.virt = 0x4010000000ULL,
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.phys = 0x4010000000ULL,
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.size = 0x10000000,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* Highmem PCI-E MMIO memory area */
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.virt = 0x8000000000ULL,
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.phys = 0x8000000000ULL,
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.size = 0x8000000000ULL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = qemu_arm64_mem_map;
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#endif
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int board_init(void)
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{
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return 0;
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}
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int board_late_init(void)
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{
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/*
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* Make sure virtio bus is enumerated so that peripherals
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* on the virtio bus can be discovered by their drivers
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*/
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virtio_init();
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return 0;
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}
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int dram_init(void)
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{
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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return 0;
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}
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int dram_init_banksize(void)
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{
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fdtdec_setup_memory_banksize();
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return 0;
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}
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void *board_fdt_blob_setup(int *err)
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{
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*err = 0;
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/* QEMU loads a generated DTB for us at the start of RAM. */
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return (void *)CONFIG_SYS_SDRAM_BASE;
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}
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void enable_caches(void)
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{
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icache_enable();
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dcache_enable();
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}
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#ifdef CONFIG_ARM64
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#define __W "w"
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#else
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#define __W
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#endif
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u8 flash_read8(void *addr)
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{
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u8 ret;
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asm("ldrb %" __W "0, %1" : "=r"(ret) : "m"(*(u8 *)addr));
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return ret;
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}
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u16 flash_read16(void *addr)
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{
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u16 ret;
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asm("ldrh %" __W "0, %1" : "=r"(ret) : "m"(*(u16 *)addr));
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return ret;
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}
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u32 flash_read32(void *addr)
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{
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u32 ret;
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asm("ldr %" __W "0, %1" : "=r"(ret) : "m"(*(u32 *)addr));
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return ret;
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}
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void flash_write8(u8 value, void *addr)
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{
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asm("strb %" __W "1, %0" : "=m"(*(u8 *)addr) : "r"(value));
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}
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void flash_write16(u16 value, void *addr)
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{
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asm("strh %" __W "1, %0" : "=m"(*(u16 *)addr) : "r"(value));
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}
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void flash_write32(u32 value, void *addr)
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{
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asm("str %" __W "1, %0" : "=m"(*(u32 *)addr) : "r"(value));
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}
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