263 lines
7.0 KiB
C
263 lines
7.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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* Author: Fabrice Gasnier <fabrice.gasnier@st.com>
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*
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* Originally based on the Linux kernel v4.18 drivers/iio/adc/stm32-adc.c.
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*/
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#include <common.h>
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#include <adc.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include "stm32-adc-core.h"
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/* STM32H7 - Registers for each ADC instance */
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#define STM32H7_ADC_ISR 0x00
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#define STM32H7_ADC_CR 0x08
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#define STM32H7_ADC_CFGR 0x0C
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#define STM32H7_ADC_SMPR1 0x14
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#define STM32H7_ADC_SMPR2 0x18
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#define STM32H7_ADC_PCSEL 0x1C
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#define STM32H7_ADC_SQR1 0x30
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#define STM32H7_ADC_DR 0x40
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#define STM32H7_ADC_DIFSEL 0xC0
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/* STM32H7_ADC_ISR - bit fields */
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#define STM32MP1_VREGREADY BIT(12)
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#define STM32H7_EOC BIT(2)
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#define STM32H7_ADRDY BIT(0)
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/* STM32H7_ADC_CR - bit fields */
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#define STM32H7_DEEPPWD BIT(29)
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#define STM32H7_ADVREGEN BIT(28)
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#define STM32H7_BOOST BIT(8)
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#define STM32H7_ADSTART BIT(2)
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#define STM32H7_ADDIS BIT(1)
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#define STM32H7_ADEN BIT(0)
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/* STM32H7_ADC_CFGR bit fields */
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#define STM32H7_EXTEN GENMASK(11, 10)
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#define STM32H7_DMNGT GENMASK(1, 0)
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/* STM32H7_ADC_SQR1 - bit fields */
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#define STM32H7_SQ1_SHIFT 6
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/* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
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#define STM32H7_BOOST_CLKRATE 20000000UL
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#define STM32_ADC_CH_MAX 20 /* max number of channels */
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#define STM32_ADC_TIMEOUT_US 100000
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struct stm32_adc_cfg {
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unsigned int max_channels;
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unsigned int num_bits;
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bool has_vregready;
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};
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struct stm32_adc {
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void __iomem *regs;
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int active_channel;
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const struct stm32_adc_cfg *cfg;
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};
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static int stm32_adc_stop(struct udevice *dev)
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{
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struct stm32_adc *adc = dev_get_priv(dev);
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADDIS);
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clrbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_BOOST);
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/* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_DEEPPWD);
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adc->active_channel = -1;
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return 0;
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}
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static int stm32_adc_start_channel(struct udevice *dev, int channel)
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{
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struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
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struct stm32_adc_common *common = dev_get_priv(dev_get_parent(dev));
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struct stm32_adc *adc = dev_get_priv(dev);
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int ret;
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u32 val;
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/* Exit deep power down, then enable ADC voltage regulator */
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clrbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_DEEPPWD);
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADVREGEN);
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if (common->rate > STM32H7_BOOST_CLKRATE)
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_BOOST);
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/* Wait for startup time */
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if (!adc->cfg->has_vregready) {
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udelay(20);
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} else {
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ret = readl_poll_timeout(adc->regs + STM32H7_ADC_ISR, val,
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val & STM32MP1_VREGREADY,
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STM32_ADC_TIMEOUT_US);
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if (ret < 0) {
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stm32_adc_stop(dev);
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dev_err(dev, "Failed to enable vreg: %d\n", ret);
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return ret;
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}
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}
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/* Only use single ended channels */
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writel(0, adc->regs + STM32H7_ADC_DIFSEL);
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/* Enable ADC, Poll for ADRDY to be set (after adc startup time) */
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADEN);
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ret = readl_poll_timeout(adc->regs + STM32H7_ADC_ISR, val,
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val & STM32H7_ADRDY, STM32_ADC_TIMEOUT_US);
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if (ret < 0) {
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stm32_adc_stop(dev);
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dev_err(dev, "Failed to enable ADC: %d\n", ret);
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return ret;
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}
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/* Preselect channels */
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writel(uc_pdata->channel_mask, adc->regs + STM32H7_ADC_PCSEL);
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/* Set sampling time to max value by default */
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writel(0xffffffff, adc->regs + STM32H7_ADC_SMPR1);
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writel(0xffffffff, adc->regs + STM32H7_ADC_SMPR2);
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/* Program regular sequence: chan in SQ1 & len = 0 for one channel */
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writel(channel << STM32H7_SQ1_SHIFT, adc->regs + STM32H7_ADC_SQR1);
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/* Trigger detection disabled (conversion can be launched in SW) */
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clrbits_le32(adc->regs + STM32H7_ADC_CFGR, STM32H7_EXTEN |
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STM32H7_DMNGT);
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adc->active_channel = channel;
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return 0;
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}
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static int stm32_adc_channel_data(struct udevice *dev, int channel,
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unsigned int *data)
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{
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struct stm32_adc *adc = dev_get_priv(dev);
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int ret;
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u32 val;
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if (channel != adc->active_channel) {
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dev_err(dev, "Requested channel is not active!\n");
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return -EINVAL;
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}
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setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADSTART);
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ret = readl_poll_timeout(adc->regs + STM32H7_ADC_ISR, val,
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val & STM32H7_EOC, STM32_ADC_TIMEOUT_US);
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if (ret < 0) {
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dev_err(dev, "conversion timed out: %d\n", ret);
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return ret;
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}
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*data = readl(adc->regs + STM32H7_ADC_DR);
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return 0;
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}
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static int stm32_adc_chan_of_init(struct udevice *dev)
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{
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struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
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struct stm32_adc *adc = dev_get_priv(dev);
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u32 chans[STM32_ADC_CH_MAX];
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unsigned int i, num_channels;
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int ret;
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/* Retrieve single ended channels listed in device tree */
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ret = dev_read_size(dev, "st,adc-channels");
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if (ret < 0) {
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dev_err(dev, "can't get st,adc-channels: %d\n", ret);
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return ret;
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}
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num_channels = ret / sizeof(u32);
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if (num_channels > adc->cfg->max_channels) {
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dev_err(dev, "too many st,adc-channels: %d\n", num_channels);
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return -EINVAL;
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}
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ret = dev_read_u32_array(dev, "st,adc-channels", chans, num_channels);
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if (ret < 0) {
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dev_err(dev, "can't read st,adc-channels: %d\n", ret);
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return ret;
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}
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for (i = 0; i < num_channels; i++) {
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if (chans[i] >= adc->cfg->max_channels) {
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dev_err(dev, "bad channel %u\n", chans[i]);
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return -EINVAL;
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}
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uc_pdata->channel_mask |= 1 << chans[i];
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}
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uc_pdata->data_mask = (1 << adc->cfg->num_bits) - 1;
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uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
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uc_pdata->data_timeout_us = 100000;
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return 0;
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}
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static int stm32_adc_probe(struct udevice *dev)
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{
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struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
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struct stm32_adc_common *common = dev_get_priv(dev_get_parent(dev));
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struct stm32_adc *adc = dev_get_priv(dev);
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int offset;
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offset = dev_read_u32_default(dev, "reg", -ENODATA);
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if (offset < 0) {
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dev_err(dev, "Can't read reg property\n");
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return offset;
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}
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adc->regs = common->base + offset;
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adc->cfg = (const struct stm32_adc_cfg *)dev_get_driver_data(dev);
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/* VDD supplied by common vref pin */
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uc_pdata->vdd_supply = common->vref;
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uc_pdata->vdd_microvolts = common->vref_uv;
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uc_pdata->vss_microvolts = 0;
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return stm32_adc_chan_of_init(dev);
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}
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static const struct adc_ops stm32_adc_ops = {
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.start_channel = stm32_adc_start_channel,
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.channel_data = stm32_adc_channel_data,
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.stop = stm32_adc_stop,
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};
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static const struct stm32_adc_cfg stm32h7_adc_cfg = {
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.num_bits = 16,
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.max_channels = STM32_ADC_CH_MAX,
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};
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static const struct stm32_adc_cfg stm32mp1_adc_cfg = {
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.num_bits = 16,
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.max_channels = STM32_ADC_CH_MAX,
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.has_vregready = true,
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};
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static const struct udevice_id stm32_adc_ids[] = {
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{ .compatible = "st,stm32h7-adc",
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.data = (ulong)&stm32h7_adc_cfg },
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{ .compatible = "st,stm32mp1-adc",
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.data = (ulong)&stm32mp1_adc_cfg },
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{}
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};
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U_BOOT_DRIVER(stm32_adc) = {
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.name = "stm32-adc",
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.id = UCLASS_ADC,
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.of_match = stm32_adc_ids,
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.probe = stm32_adc_probe,
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.ops = &stm32_adc_ops,
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.priv_auto = sizeof(struct stm32_adc),
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};
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