382 lines
8.9 KiB
C
382 lines
8.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2021 ASPEED Technology Inc.
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*/
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#include <config.h>
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#include <common.h>
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#include <dm.h>
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#include <clk.h>
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#include <log.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <watchdog.h>
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#include <u-boot/hash.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/iopoll.h>
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/* register offsets*/
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#define HACE_STS 0x1C
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#define HACE_HASH_DATA_OVF BIT(23)
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#define HACE_HASH_INT BIT(9)
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#define HACE_HASH_BUSY BIT(0)
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#define HACE_HASH_DATA 0x20
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#define HACE_HASH_DIGEST 0x24
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#define HACE_HASH_HMAC_KEY 0x28
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#define HACE_HASH_DATA_LEN 0x2C
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#define HACE_HASH_CMD 0x30
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#define HACE_HASH_MODE_ACCUM BIT(8)
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#define HACE_HASH_ALGO_SHA1 BIT(5)
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#define HACE_HASH_ALGO_SHA256 (BIT(6) | BIT(4))
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#define HACE_HASH_ALGO_SHA384 (BIT(10) | BIT(6) | BIT(5))
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#define HACE_HASH_ALGO_SHA512 (BIT(6) | BIT(5))
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#define HACE_HASH_SHA_BE_EN BIT(3)
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/* buffer size based on SHA-512 need*/
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#define HASH_BLOCK_BUFSZ 128
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#define HASH_DIGEST_BUFSZ 64
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struct aspeed_hace_ctx {
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uint8_t digest[HASH_DIGEST_BUFSZ];
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uint32_t cmd;
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enum HASH_ALGO algo;
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uint32_t blk_size;
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uint32_t pad_size;
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uint64_t total[2];
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uint8_t buf[HASH_BLOCK_BUFSZ];
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uint32_t buf_cnt;
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} __aligned((8));
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struct aspeed_hace {
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phys_addr_t base;
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struct clk clk;
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};
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static const uint32_t iv_sha1[8] = {
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0x01234567, 0x89abcdef, 0xfedcba98, 0x76543210,
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0xf0e1d2c3, 0, 0, 0
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};
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static const uint32_t iv_sha256[8] = {
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0x67e6096a, 0x85ae67bb, 0x72f36e3c, 0x3af54fa5,
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0x7f520e51, 0x8c68059b, 0xabd9831f, 0x19cde05bUL
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};
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static const uint32_t iv_sha384[16] = {
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0x5d9dbbcb, 0xd89e05c1, 0x2a299a62, 0x07d57c36,
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0x5a015991, 0x17dd7030, 0xd8ec2f15, 0x39590ef7,
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0x67263367, 0x310bc0ff, 0x874ab48e, 0x11155868,
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0x0d2e0cdb, 0xa78ff964, 0x1d48b547, 0xa44ffabeUL
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};
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static const uint32_t iv_sha512[16] = {
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0x67e6096a, 0x08c9bcf3, 0x85ae67bb, 0x3ba7ca84,
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0x72f36e3c, 0x2bf894fe, 0x3af54fa5, 0xf1361d5f,
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0x7f520e51, 0xd182e6ad, 0x8c68059b, 0x1f6c3e2b,
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0xabd9831f, 0x6bbd41fb, 0x19cde05b, 0x79217e13UL
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};
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static int aspeed_hace_wait_completion(uint32_t reg, uint32_t flag, int timeout_us)
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{
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uint32_t val;
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return readl_poll_timeout(reg, val, (val & flag) == flag, timeout_us);
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}
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static int aspeed_hace_process(struct udevice *dev, void *ctx, const void *ibuf, uint32_t ilen)
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{
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struct aspeed_hace *hace = dev_get_priv(dev);
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struct aspeed_hace_ctx *hace_ctx = (struct aspeed_hace_ctx *)ctx;
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uint32_t sts = readl(hace->base + HACE_STS);
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if (sts & HACE_HASH_BUSY) {
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debug("HACE engine busy\n");
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return -EBUSY;
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}
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writel(HACE_HASH_INT, hace->base + HACE_STS);
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writel((uint32_t)ibuf, hace->base + HACE_HASH_DATA);
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writel((uint32_t)hace_ctx->digest, hace->base + HACE_HASH_DIGEST);
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writel((uint32_t)hace_ctx->digest, hace->base + HACE_HASH_HMAC_KEY);
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writel(ilen, hace->base + HACE_HASH_DATA_LEN);
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writel(hace_ctx->cmd, hace->base + HACE_HASH_CMD);
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return aspeed_hace_wait_completion(hace->base + HACE_STS,
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HACE_HASH_INT,
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1000 + (ilen >> 3));
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}
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static int aspeed_hace_init(struct udevice *dev, enum HASH_ALGO algo, void **ctxp)
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{
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struct aspeed_hace_ctx *hace_ctx;
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hace_ctx = memalign(8, sizeof(struct aspeed_hace_ctx));
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if (!hace_ctx)
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return -ENOMEM;
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memset(hace_ctx, 0, sizeof(struct aspeed_hace_ctx));
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hace_ctx->algo = algo;
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hace_ctx->cmd = HACE_HASH_MODE_ACCUM | HACE_HASH_SHA_BE_EN;
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switch (algo) {
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case HASH_ALGO_SHA1:
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hace_ctx->blk_size = 64;
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hace_ctx->pad_size = 8;
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hace_ctx->cmd |= HACE_HASH_ALGO_SHA1;
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memcpy(hace_ctx->digest, iv_sha1, sizeof(iv_sha1));
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break;
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case HASH_ALGO_SHA256:
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hace_ctx->blk_size = 64;
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hace_ctx->pad_size = 8;
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hace_ctx->cmd |= HACE_HASH_ALGO_SHA256;
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memcpy(hace_ctx->digest, iv_sha256, sizeof(iv_sha256));
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break;
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case HASH_ALGO_SHA384:
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hace_ctx->blk_size = 128;
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hace_ctx->pad_size = 16;
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hace_ctx->cmd |= HACE_HASH_ALGO_SHA384;
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memcpy(hace_ctx->digest, iv_sha384, sizeof(iv_sha384));
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break;
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case HASH_ALGO_SHA512:
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hace_ctx->blk_size = 128;
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hace_ctx->pad_size = 16;
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hace_ctx->cmd |= HACE_HASH_ALGO_SHA512;
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memcpy(hace_ctx->digest, iv_sha512, sizeof(iv_sha512));
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break;
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default:
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debug("Unsupported hash algorithm '%s'\n", hash_algo_name(algo));
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goto free_n_out;
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};
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*ctxp = hace_ctx;
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return 0;
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free_n_out:
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free(hace_ctx);
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return -EINVAL;
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}
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static int aspeed_hace_update(struct udevice *dev, void *ctx, const void *ibuf, uint32_t ilen)
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{
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int rc;
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uint32_t left, fill;
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struct aspeed_hace_ctx *hace_ctx = ctx;
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left = hace_ctx->total[0] & (hace_ctx->blk_size - 1);
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fill = hace_ctx->blk_size - left;
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hace_ctx->total[0] += ilen;
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if (hace_ctx->total[0] < ilen)
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hace_ctx->total[1]++;
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if (left && ilen >= fill) {
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memcpy(hace_ctx->buf + left, ibuf, fill);
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rc = aspeed_hace_process(dev, ctx, hace_ctx->buf, hace_ctx->blk_size);
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if (rc) {
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debug("failed to process hash, rc=%d\n", rc);
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return rc;
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}
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ilen -= fill;
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ibuf += fill;
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left = 0;
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}
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while (ilen >= hace_ctx->blk_size) {
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rc = aspeed_hace_process(dev, ctx, ibuf, hace_ctx->blk_size);
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if (rc) {
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debug("failed to process hash, rc=%d\n", rc);
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return rc;
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}
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ibuf += hace_ctx->blk_size;
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ilen -= hace_ctx->blk_size;
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}
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if (ilen)
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memcpy(hace_ctx->buf + left, ibuf, ilen);
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return 0;
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}
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static int aspeed_hace_finish(struct udevice *dev, void *ctx, void *obuf)
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{
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int rc = 0;
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uint8_t pad[HASH_BLOCK_BUFSZ * 2];
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uint32_t last, padn;
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uint64_t ibits_h, ibits_l;
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uint64_t ibits_be_h, ibits_be_l;
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struct aspeed_hace_ctx *hace_ctx = ctx;
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memset(pad, 0, sizeof(pad));
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pad[0] = 0x80;
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ibits_h = (hace_ctx->total[0] >> 61) | (hace_ctx->total[1] << 3);
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ibits_be_h = cpu_to_be64(ibits_h);
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ibits_l = (hace_ctx->total[0] << 3);
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ibits_be_l = cpu_to_be64(ibits_l);
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last = hace_ctx->total[0] & (hace_ctx->blk_size - 1);
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switch (hace_ctx->algo) {
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case HASH_ALGO_SHA1:
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case HASH_ALGO_SHA256:
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padn = (last < 56) ? (56 - last) : (120 - last);
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rc = aspeed_hace_update(dev, ctx, pad, padn);
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if (rc) {
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debug("failed to append padding, rc=%d\n", rc);
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goto free_n_out;
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}
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rc = aspeed_hace_update(dev, ctx, &ibits_be_l, sizeof(ibits_be_l));
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if (rc) {
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debug("failed to append message bits length, rc=%d\n", rc);
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goto free_n_out;
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}
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break;
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case HASH_ALGO_SHA384:
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case HASH_ALGO_SHA512:
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padn = (last < 112) ? (112 - last) : (240 - last);
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rc = aspeed_hace_update(dev, ctx, pad, padn);
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if (rc) {
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debug("failed to append padding, rc=%d\n", rc);
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goto free_n_out;
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}
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rc = aspeed_hace_update(dev, ctx, &ibits_be_h, sizeof(ibits_be_h)) |
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aspeed_hace_update(dev, ctx, &ibits_be_l, sizeof(ibits_be_l));
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if (rc) {
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debug("failed to append message bits length, rc=%d\n", rc);
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goto free_n_out;
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}
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break;
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default:
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rc = -EINVAL;
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break;
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}
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memcpy(obuf, hace_ctx->digest, hash_algo_digest_size(hace_ctx->algo));
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free_n_out:
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free(ctx);
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return rc;
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}
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static int aspeed_hace_digest_wd(struct udevice *dev, enum HASH_ALGO algo,
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const void *ibuf, const uint32_t ilen,
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void *obuf, uint32_t chunk_sz)
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{
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int rc;
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void *ctx;
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const void *cur, *end;
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uint32_t chunk;
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rc = aspeed_hace_init(dev, algo, &ctx);
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if (rc)
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return rc;
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if (CONFIG_IS_ENABLED(HW_WATCHDOG) || CONFIG_IS_ENABLED(WATCHDOG)) {
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cur = ibuf;
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end = ibuf + ilen;
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while (cur < end) {
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chunk = end - cur;
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if (chunk > chunk_sz)
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chunk = chunk_sz;
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rc = aspeed_hace_update(dev, ctx, cur, chunk);
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if (rc)
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return rc;
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cur += chunk;
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WATCHDOG_RESET();
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}
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} else {
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rc = aspeed_hace_update(dev, ctx, ibuf, ilen);
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if (rc)
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return rc;
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}
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rc = aspeed_hace_finish(dev, ctx, obuf);
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if (rc)
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return rc;
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return 0;
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}
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static int aspeed_hace_digest(struct udevice *dev, enum HASH_ALGO algo,
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const void *ibuf, const uint32_t ilen,
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void *obuf)
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{
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/* re-use the watchdog version with input length as the chunk_sz */
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return aspeed_hace_digest_wd(dev, algo, ibuf, ilen, obuf, ilen);
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}
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static int aspeed_hace_probe(struct udevice *dev)
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{
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int rc;
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struct aspeed_hace *hace = dev_get_priv(dev);
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rc = clk_get_by_index(dev, 0, &hace->clk);
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if (rc < 0) {
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debug("cannot get clock for %s: %d\n", dev->name, rc);
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return rc;
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}
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rc = clk_enable(&hace->clk);
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if (rc) {
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debug("cannot enable clock for %s: %d\n", dev->name, rc);
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return rc;
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}
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hace->base = devfdt_get_addr(dev);
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return rc;
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}
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static int aspeed_hace_remove(struct udevice *dev)
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{
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struct aspeed_hace *hace = dev_get_priv(dev);
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clk_disable(&hace->clk);
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return 0;
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}
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static const struct hash_ops aspeed_hace_ops = {
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.hash_init = aspeed_hace_init,
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.hash_update = aspeed_hace_update,
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.hash_finish = aspeed_hace_finish,
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.hash_digest_wd = aspeed_hace_digest_wd,
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.hash_digest = aspeed_hace_digest,
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};
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static const struct udevice_id aspeed_hace_ids[] = {
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{ .compatible = "aspeed,ast2600-hace" },
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{ }
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};
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U_BOOT_DRIVER(aspeed_hace) = {
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.name = "aspeed_hace",
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.id = UCLASS_HASH,
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.of_match = aspeed_hace_ids,
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.ops = &aspeed_hace_ops,
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.probe = aspeed_hace_probe,
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.remove = aspeed_hace_remove,
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.priv_auto = sizeof(struct aspeed_hace),
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.flags = DM_FLAG_PRE_RELOC,
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};
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