87 lines
3.3 KiB
C
87 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _DDR3_TRAINING_IP_ENGINE_H_
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#define _DDR3_TRAINING_IP_ENGINE_H_
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#include "ddr3_training_ip_def.h"
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#include "ddr3_training_ip_flow.h"
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#include "ddr3_training_ip_pbs.h"
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#define EDGE_1 0
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#define EDGE_2 1
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#define ALL_PUP_TRAINING 0xe
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#define PUP_RESULT_EDGE_1_MASK 0xff
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#define PUP_RESULT_EDGE_2_MASK (0xff << 8)
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#define PUP_LOCK_RESULT_BIT 25
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#define GET_TAP_RESULT(reg, edge) \
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(((edge) == EDGE_1) ? ((reg) & PUP_RESULT_EDGE_1_MASK) : \
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(((reg) & PUP_RESULT_EDGE_2_MASK) >> 8));
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#define GET_LOCK_RESULT(reg) \
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(((reg) & (1<<PUP_LOCK_RESULT_BIT)) >> PUP_LOCK_RESULT_BIT)
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#define EDGE_FAILURE 128
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#define ALL_BITS_PER_PUP 128
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#define MIN_WINDOW_SIZE 6
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#define MAX_WINDOW_SIZE_RX 32
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#define MAX_WINDOW_SIZE_TX 64
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int ddr3_tip_training_ip_test(u32 dev_num, enum hws_training_result result_type,
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enum hws_search_dir search_dir,
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enum hws_dir direction,
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enum hws_edge_compare edge,
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u32 init_val1, u32 init_val2,
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u32 num_of_iterations, u32 start_pattern,
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u32 end_pattern);
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int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern pattern);
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int ddr3_tip_load_all_pattern_to_mem(u32 dev_num);
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int ddr3_tip_read_training_result(u32 dev_num, u32 if_id,
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enum hws_access_type pup_access_type,
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u32 pup_num, u32 bit_num,
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enum hws_search_dir search,
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enum hws_dir direction,
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enum hws_training_result result_type,
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enum hws_training_load_op operation,
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u32 cs_num_type, u32 **load_res,
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int is_read_from_db, u8 cons_tap,
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int is_check_result_validity);
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int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type,
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u32 interface_num,
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enum hws_access_type pup_access_type,
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u32 pup_num, enum hws_training_result result_type,
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enum hws_control_element control_element,
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enum hws_search_dir search_dir, enum hws_dir direction,
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u32 interface_mask, u32 init_value, u32 num_iter,
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enum hws_pattern pattern,
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enum hws_edge_compare edge_comp,
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enum hws_ddr_cs cs_type, u32 cs_num,
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enum hws_training_ip_stat *train_status);
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int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type,
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u32 if_id,
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enum hws_access_type pup_access_type,
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u32 pup_num,
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enum hws_training_result result_type,
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enum hws_control_element control_element,
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enum hws_search_dir search_dir,
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enum hws_dir direction,
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u32 interface_mask, u32 init_value1,
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u32 init_value2, u32 num_iter,
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enum hws_pattern pattern,
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enum hws_edge_compare edge_comp,
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enum hws_ddr_cs train_cs_type, u32 cs_num,
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enum hws_training_ip_stat *train_status);
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u8 mv_ddr_tip_sub_phy_byte_status_get(u32 if_id, u32 subphy_id);
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void mv_ddr_tip_sub_phy_byte_status_set(u32 if_id, u32 subphy_id, u8 byte_status_data);
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void ddr3_tip_print_bist_res(void);
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struct pattern_info *ddr3_tip_get_pattern_table(void);
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u16 *ddr3_tip_get_mask_results_dq_reg(void);
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u16 *ddr3_tip_get_mask_results_pup_reg_map(void);
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int mv_ddr_load_dm_pattern_to_odpg(enum hws_access_type access_type, enum hws_pattern pattern,
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enum dm_direction dm_dir);
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int mv_ddr_pattern_start_addr_set(struct pattern_info *pattern_tbl, enum hws_pattern pattern, u32 addr);
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#endif /* _DDR3_TRAINING_IP_ENGINE_H_ */
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