547 lines
14 KiB
C
547 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2020
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* Tim Harvey, Gateworks Corporation
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*/
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <eth_phy.h>
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#include <linux/delay.h>
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#include <miiphy.h>
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#include <i2c.h>
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#include <net/dsa.h>
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#include <asm-generic/gpio.h>
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/* Global registers */
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/* Chip ID */
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#define REG_CHIP_ID0__1 0x0000
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/* Operation control */
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#define REG_SW_OPERATION 0x0300
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#define SW_RESET BIT(1)
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#define SW_START BIT(0)
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/* Port Specific Registers */
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#define PORT_CTRL_ADDR(port, addr) ((addr) | (((port) + 1) << 12))
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/* Port Control */
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#define REG_PORT_XMII_CTRL_1 0x0301
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#define PORT_MII_NOT_1GBIT BIT(6)
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#define PORT_MII_SEL_EDGE BIT(5)
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#define PORT_RGMII_ID_IG_ENABLE BIT(4)
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#define PORT_RGMII_ID_EG_ENABLE BIT(3)
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#define PORT_MII_MAC_MODE BIT(2)
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#define PORT_MII_SEL_M 0x3
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#define PORT_RGMII_SEL 0x0
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#define PORT_RMII_SEL 0x1
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#define PORT_GMII_SEL 0x2
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#define PORT_MII_SEL 0x3
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/* Port MSTP State Register */
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#define REG_PORT_MSTP_STATE 0x0b04
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#define PORT_TX_ENABLE BIT(2)
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#define PORT_RX_ENABLE BIT(1)
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#define PORT_LEARN_DISABLE BIT(0)
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/* MMD */
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#define REG_PORT_PHY_MMD_SETUP 0x011A
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#define PORT_MMD_OP_MODE_M 0x3
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#define PORT_MMD_OP_MODE_S 14
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#define PORT_MMD_OP_INDEX 0
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#define PORT_MMD_OP_DATA_NO_INCR 1
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#define PORT_MMD_OP_DATA_INCR_RW 2
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#define PORT_MMD_OP_DATA_INCR_W 3
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#define PORT_MMD_DEVICE_ID_M 0x1F
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#define MMD_SETUP(mode, dev) (((u16)(mode) << PORT_MMD_OP_MODE_S) | (dev))
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#define REG_PORT_PHY_MMD_INDEX_DATA 0x011C
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struct ksz_dsa_priv {
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struct udevice *dev;
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int active_port;
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};
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static inline int ksz_read8(struct udevice *dev, u32 reg, u8 *val)
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{
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int ret = dm_i2c_read(dev, reg, val, 1);
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dev_dbg(dev, "%s 0x%04x<<0x%02x\n", __func__, reg, *val);
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return ret;
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}
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static inline int ksz_pread8(struct udevice *dev, int port, int reg, u8 *val)
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{
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return ksz_read8(dev, PORT_CTRL_ADDR(port, reg), val);
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}
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static inline int ksz_write8(struct udevice *dev, u32 reg, u8 val)
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{
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dev_dbg(dev, "%s 0x%04x>>0x%02x\n", __func__, reg, val);
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return dm_i2c_write(dev, reg, &val, 1);
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}
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static inline int ksz_pwrite8(struct udevice *dev, int port, int reg, u8 val)
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{
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return ksz_write8(dev, PORT_CTRL_ADDR(port, reg), val);
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}
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static inline int ksz_write16(struct udevice *dev, u32 reg, u16 val)
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{
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u8 buf[2];
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buf[1] = val & 0xff;
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buf[0] = val >> 8;
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dev_dbg(dev, "%s 0x%04x>>0x%04x\n", __func__, reg, val);
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return dm_i2c_write(dev, reg, buf, 2);
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}
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static inline int ksz_pwrite16(struct udevice *dev, int port, int reg, u16 val)
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{
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return ksz_write16(dev, PORT_CTRL_ADDR(port, reg), val);
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}
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static inline int ksz_read16(struct udevice *dev, u32 reg, u16 *val)
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{
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u8 buf[2];
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int ret;
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ret = dm_i2c_read(dev, reg, buf, 2);
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*val = (buf[0] << 8) | buf[1];
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dev_dbg(dev, "%s 0x%04x<<0x%04x\n", __func__, reg, *val);
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return ret;
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}
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static inline int ksz_pread16(struct udevice *dev, int port, int reg, u16 *val)
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{
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return ksz_read16(dev, PORT_CTRL_ADDR(port, reg), val);
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}
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static inline int ksz_read32(struct udevice *dev, u32 reg, u32 *val)
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{
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return dm_i2c_read(dev, reg, (u8 *)val, 4);
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}
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static inline int ksz_pread32(struct udevice *dev, int port, int reg, u32 *val)
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{
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return ksz_read32(dev, PORT_CTRL_ADDR(port, reg), val);
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}
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static inline int ksz_write32(struct udevice *dev, u32 reg, u32 val)
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{
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u8 buf[4];
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buf[3] = val & 0xff;
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buf[2] = (val >> 24) & 0xff;
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buf[1] = (val >> 16) & 0xff;
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buf[0] = (val >> 8) & 0xff;
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dev_dbg(dev, "%s 0x%04x>>0x%04x\n", __func__, reg, val);
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return dm_i2c_write(dev, reg, buf, 4);
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}
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static inline int ksz_pwrite32(struct udevice *dev, int port, int reg, u32 val)
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{
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return ksz_write32(dev, PORT_CTRL_ADDR(port, reg), val);
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}
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static __maybe_unused void ksz_port_mmd_read(struct udevice *dev, int port,
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u8 addr, u16 reg, u16 *val)
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{
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ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, MMD_SETUP(PORT_MMD_OP_INDEX, addr));
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ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg);
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ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, addr));
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ksz_pread16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val);
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dev_dbg(dev, "%s P%d 0x%02x:0x%04x<<0x%04x\n", __func__, port + 1, addr, reg, *val);
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}
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static void ksz_port_mmd_write(struct udevice *dev, int port, u8 addr, u16 reg, u16 val)
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{
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dev_dbg(dev, "%s P%d 0x%02x:0x%04x>>0x%04x\n", __func__, port + 1, addr, addr, val);
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ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, MMD_SETUP(PORT_MMD_OP_INDEX, addr));
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ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, addr);
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ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, addr));
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ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val);
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}
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/* Apply PHY settings to address errata listed in KSZ9477, KSZ9897, KSZ9896, KSZ9567
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* Silicon Errata and Data Sheet Clarification documents
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*/
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static void ksz_phy_errata_setup(struct udevice *dev, int port)
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{
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dev_dbg(dev, "%s P%d\n", __func__, port + 1);
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/* Register settings are needed to improve PHY receive performance */
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ksz_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b);
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ksz_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032);
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ksz_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c);
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ksz_port_mmd_write(dev, port, 0x01, 0x75, 0x0060);
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ksz_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777);
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ksz_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008);
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ksz_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001);
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/* Transmit waveform amplitude can be improved (1000BASE-T, 100BASE-TX, 10BASE-Te) */
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ksz_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0);
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/* Energy Efficient Ethernet (EEE) feature select must be manually disabled */
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ksz_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000);
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/* Register settings are required to meet data sheet supply current specifications */
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ksz_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff);
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ksz_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff);
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ksz_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff);
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ksz_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff);
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ksz_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff);
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ksz_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff);
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ksz_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff);
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ksz_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff);
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ksz_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff);
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ksz_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff);
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ksz_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff);
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ksz_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff);
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ksz_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee);
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}
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/*
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* mii bus driver
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*/
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#define KSZ_MDIO_CHILD_DRV_NAME "ksz_mdio"
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struct ksz_mdio_priv {
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struct ksz_dsa_priv *ksz;
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};
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static int dm_ksz_mdio_read(struct udevice *dev, int addr, int devad, int reg)
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{
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struct ksz_mdio_priv *priv = dev_get_priv(dev);
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struct ksz_dsa_priv *ksz = priv->ksz;
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u16 val = 0xffff;
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ksz_pread16(ksz->dev, addr, 0x100 + (reg << 1), &val);
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dev_dbg(ksz->dev, "%s P%d reg=0x%04x:0x%04x<<0x%04x\n", __func__,
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addr + 1, reg, 0x100 + (reg << 1), val);
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return val;
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};
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static int dm_ksz_mdio_write(struct udevice *dev, int addr, int devad, int reg, u16 val)
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{
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struct ksz_mdio_priv *priv = dev_get_priv(dev);
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struct ksz_dsa_priv *ksz = priv->ksz;
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dev_dbg(ksz->dev, "%s P%d reg=0x%04x:%04x>>0x%04x\n",
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__func__, addr + 1, reg, 0x100 + (reg << 1), val);
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ksz_pwrite16(ksz->dev, addr, 0x100 + (reg << 1), val);
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return 0;
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}
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static const struct mdio_ops ksz_mdio_ops = {
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.read = dm_ksz_mdio_read,
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.write = dm_ksz_mdio_write,
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};
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static int ksz_mdio_bind(struct udevice *dev)
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{
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char name[16];
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static int num_devices;
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dev_dbg(dev, "%s\n", __func__);
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sprintf(name, "ksz-mdio-%d", num_devices++);
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device_set_name(dev, name);
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return 0;
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}
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static int ksz_mdio_probe(struct udevice *dev)
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{
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struct ksz_mdio_priv *priv = dev_get_priv(dev);
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dev_dbg(dev, "%s\n", __func__);
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priv->ksz = dev_get_parent_priv(dev->parent);
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return 0;
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}
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static const struct udevice_id ksz_mdio_ids[] = {
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{ .compatible = "microchip,ksz-mdio" },
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{ }
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};
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U_BOOT_DRIVER(ksz_mdio) = {
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.name = KSZ_MDIO_CHILD_DRV_NAME,
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.id = UCLASS_MDIO,
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.of_match = ksz_mdio_ids,
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.bind = ksz_mdio_bind,
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.probe = ksz_mdio_probe,
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.ops = &ksz_mdio_ops,
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.priv_auto = sizeof(struct ksz_mdio_priv),
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.plat_auto = sizeof(struct mdio_perdev_priv),
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};
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static int ksz_port_setup(struct udevice *dev, int port,
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phy_interface_t interface)
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{
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struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
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u8 data8;
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dev_dbg(dev, "%s P%d %s\n", __func__, port + 1,
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(port == pdata->cpu_port) ? "cpu" : "");
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if (port != pdata->cpu_port) {
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/* phy port: config errata and leds */
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ksz_phy_errata_setup(dev, port);
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} else {
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/* cpu port: configure MAC interface mode */
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ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
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dev_dbg(dev, "%s P%d cpu interface %s\n", __func__, port + 1,
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phy_string_for_interface(interface));
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switch (interface) {
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case PHY_INTERFACE_MODE_MII:
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data8 &= ~PORT_MII_SEL_M;
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data8 |= PORT_MII_SEL;
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data8 |= PORT_MII_NOT_1GBIT;
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break;
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case PHY_INTERFACE_MODE_RMII:
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data8 &= ~PORT_MII_SEL_M;
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data8 |= PORT_RMII_SEL;
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data8 |= PORT_MII_NOT_1GBIT;
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break;
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case PHY_INTERFACE_MODE_GMII:
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data8 &= ~PORT_MII_SEL_M;
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data8 |= PORT_GMII_SEL;
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data8 &= ~PORT_MII_NOT_1GBIT;
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break;
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default:
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data8 &= ~PORT_MII_SEL_M;
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data8 |= PORT_RGMII_SEL;
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data8 &= ~PORT_MII_NOT_1GBIT;
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data8 &= ~PORT_RGMII_ID_IG_ENABLE;
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data8 &= ~PORT_RGMII_ID_EG_ENABLE;
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if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
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interface == PHY_INTERFACE_MODE_RGMII_RXID)
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data8 |= PORT_RGMII_ID_IG_ENABLE;
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if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
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interface == PHY_INTERFACE_MODE_RGMII_TXID)
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data8 |= PORT_RGMII_ID_EG_ENABLE;
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break;
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}
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ksz_write8(dev, PORT_CTRL_ADDR(port, REG_PORT_XMII_CTRL_1), data8);
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}
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return 0;
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}
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static int ksz_port_enable(struct udevice *dev, int port, struct phy_device *phy)
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{
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struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
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struct ksz_dsa_priv *priv = dev_get_priv(dev);
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int supported = PHY_GBIT_FEATURES;
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u8 data8;
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int ret;
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dev_dbg(dev, "%s P%d 0x%x %s\n", __func__, port + 1, phy->phy_id,
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phy_string_for_interface(phy->interface));
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/* setup this port */
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ret = ksz_port_setup(dev, port, phy->interface);
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if (ret) {
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dev_err(dev, "port setup failed: %d\n", ret);
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return ret;
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}
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/* enable port forwarding for this port */
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ksz_pread8(priv->dev, port, REG_PORT_MSTP_STATE, &data8);
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data8 &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
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data8 |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
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ksz_pwrite8(priv->dev, port, REG_PORT_MSTP_STATE, data8);
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/* if cpu master we are done */
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if (port == pdata->cpu_port)
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return 0;
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/* configure phy */
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phy->supported &= supported;
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phy->advertising &= supported;
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ret = phy_config(phy);
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if (ret)
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return ret;
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ret = phy_startup(phy);
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if (ret)
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return ret;
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/* start switch */
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ksz_read8(priv->dev, REG_SW_OPERATION, &data8);
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data8 |= SW_START;
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ksz_write8(priv->dev, REG_SW_OPERATION, data8);
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/* keep track of current enabled non-cpu port */
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priv->active_port = port;
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return 0;
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}
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static void ksz_port_disable(struct udevice *dev, int port, struct phy_device *phy)
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{
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struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
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struct ksz_dsa_priv *priv = dev_get_priv(dev);
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u8 data8;
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dev_dbg(dev, "%s P%d 0x%x\n", __func__, port + 1, phy->phy_id);
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/* can't disable CPU port without re-configuring/re-starting switch */
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if (port == pdata->cpu_port)
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return;
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/* disable port */
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ksz_pread8(priv->dev, port, REG_PORT_MSTP_STATE, &data8);
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data8 &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
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data8 |= PORT_LEARN_DISABLE;
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ksz_pwrite8(priv->dev, port, REG_PORT_MSTP_STATE, data8);
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/*
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* we don't call phy_shutdown here to avoid waiting next time we use
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* the port, but the downside is that remote side will think we're
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* actively processing traffic although we are not.
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*/
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}
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static int ksz_xmit(struct udevice *dev, int port, void *packet, int length)
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{
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dev_dbg(dev, "%s P%d %d\n", __func__, port + 1, length);
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return 0;
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}
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static int ksz_recv(struct udevice *dev, int *port, void *packet, int length)
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{
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struct ksz_dsa_priv *priv = dev_get_priv(dev);
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dev_dbg(dev, "%s P%d %d\n", __func__, priv->active_port + 1, length);
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*port = priv->active_port;
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return 0;
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};
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static const struct dsa_ops ksz_dsa_ops = {
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.port_enable = ksz_port_enable,
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.port_disable = ksz_port_disable,
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.xmit = ksz_xmit,
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|
.rcv = ksz_recv,
|
|
};
|
|
|
|
static int ksz_probe_mdio(struct udevice *dev)
|
|
{
|
|
ofnode node, mdios;
|
|
int ret;
|
|
|
|
mdios = dev_read_subnode(dev, "mdios");
|
|
if (ofnode_valid(mdios)) {
|
|
ofnode_for_each_subnode(node, mdios) {
|
|
const char *name = ofnode_get_name(node);
|
|
struct udevice *pdev;
|
|
|
|
ret = device_bind_driver_to_node(dev,
|
|
KSZ_MDIO_CHILD_DRV_NAME,
|
|
name, node, &pdev);
|
|
if (ret)
|
|
dev_err(dev, "failed to probe %s: %d\n", name, ret);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* I2C driver
|
|
*/
|
|
static int ksz_i2c_probe(struct udevice *dev)
|
|
{
|
|
struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
|
|
struct ksz_dsa_priv *priv = dev_get_priv(dev);
|
|
struct udevice *master = dsa_get_master(dev);
|
|
int i, ret;
|
|
u8 data8;
|
|
u32 id;
|
|
|
|
if (!master)
|
|
return -ENODEV;
|
|
|
|
dev_dbg(dev, "%s %s master:%s\n", __func__, dev->name, master->name);
|
|
dev_set_parent_priv(dev, priv);
|
|
|
|
ret = i2c_set_chip_offset_len(dev, 2);
|
|
if (ret) {
|
|
printf("i2c_set_chip_offset_len failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
/* default config */
|
|
priv->dev = dev;
|
|
|
|
/* chip level reset */
|
|
ksz_read8(priv->dev, REG_SW_OPERATION, &data8);
|
|
data8 |= SW_RESET;
|
|
ksz_write8(priv->dev, REG_SW_OPERATION, data8);
|
|
|
|
/* read chip id */
|
|
ret = ksz_read32(dev, REG_CHIP_ID0__1, &id);
|
|
if (ret)
|
|
return ret;
|
|
id = __swab32(id);
|
|
dev_dbg(dev, "%s id=0x%08x\n", __func__, id);
|
|
switch (id & 0xffffff00) {
|
|
case 0x00947700:
|
|
puts("KSZ9477S: ");
|
|
break;
|
|
case 0x00956700:
|
|
puts("KSZ9567R: ");
|
|
break;
|
|
case 0x00989700:
|
|
puts("KSZ9897S: ");
|
|
break;
|
|
default:
|
|
dev_err(dev, "invalid chip id: 0x%08x\n", id);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* probe mdio bus */
|
|
ret = ksz_probe_mdio(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* disable ports by default */
|
|
for (i = 0; i < pdata->num_ports; i++) {
|
|
ksz_pread8(priv->dev, i, REG_PORT_MSTP_STATE, &data8);
|
|
data8 &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
|
|
ksz_pwrite8(priv->dev, i, REG_PORT_MSTP_STATE, data8);
|
|
}
|
|
|
|
dsa_set_tagging(dev, 0, 0);
|
|
|
|
return 0;
|
|
};
|
|
|
|
static const struct udevice_id ksz_i2c_ids[] = {
|
|
{ .compatible = "microchip,ksz9897" },
|
|
{ .compatible = "microchip,ksz9477" },
|
|
{ .compatible = "microchip,ksz9567" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(ksz) = {
|
|
.name = "ksz-switch",
|
|
.id = UCLASS_DSA,
|
|
.of_match = ksz_i2c_ids,
|
|
.probe = ksz_i2c_probe,
|
|
.ops = &ksz_dsa_ops,
|
|
.priv_auto = sizeof(struct ksz_dsa_priv),
|
|
};
|